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TS83C51RD2-MIA中文资料

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1.Features
•80C52Compatible
–8051pinandinstructioncompatible–Four8-bitI/Oports
–Three16-bittimer/counters–256bytesscratchpadRAM•
High-SpeedArchitecture
–40MHz@5V,30MHz@3V
–X2SpeedImprovementcapability(6clocks/machinecycle–30MHz@5V,20MHz@3V(Equivalentto–60MHz@5V,40MHz@3V•DualDataPointer
•On-chipROM/EPROM(16K-bytes,32K-bytes,64K-bytes•On-chipeXpandedRAM(XRAM(256or768bytes
•ProgrammableClockOutandUp/DownTimer/Counter2•
ProgrammableCounterArraywith–HighSpeedOutput,–Compare/Capture,–PulseWidthModulator,
–WatchdogTimerCapabilities
•HardwareWatchdogTimer(One-timeenabledwithReset-Out
•2extra8-bitI/OportsavailableonRD2withhighpincountpackages•Asynchronousportreset•
InterruptStructurewith–7Interruptsources,
–4levelpriorityinterruptsystem•
FullduplexEnhancedUART–Framingerrordetection
–Automaticaddressrecognition•LowEMI(inhibitALE•
PowerControlmodes–Idlemode
–Power-downmode–Power-offFlag
•Oncemode(On-chipEmulation•Powersupply:4.5-5V,2.7-5.5V
•Temperatureranges:Commercial(0to70oCandIndustrial(-40to85oC•
Packages:PDIL40,PLCC44,VQFP441.4,PLCC68,VQFP641.4
2.Description
AtmelTS8xC51Rx2isahighperformanceCMOSROM,OTP,EPROMandROMlessversionsofthe80C51CMOSsinglechip8-bitmicrocontroller.
TheTS8xC51Rx2retainsallfeaturesofthe80C51withextendedROM/EPROMcapacity(16/32/64Kbytes,256bytesofinternalRAM,a7-source,4-levelinterruptsystem,anon-chiposcilatorandthreetimer/counters.
Inaddition,theTS80C51Rx2hasaProgrammableCounterArray,anXRAMof256or768bytes,aHardwareWatchdogTimer,amoreversatileserialchannelthatfacili-
High
Performance8-bit
Microcontroller
TS80C51RA2TS80C51RD2TS83C51RB2TS83C51RC2TS83C51RD2TS87C51RB2TS87C51RC2TS87C51RD2AT80C51RA2AT80C51RD2AT83C51RB2AT83C51RC2AT83C51RD2AT87C51RB2AT87C51RC2AT87C51RD2
Rev.4188E–8051–08/06

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tatesmultiprocessorcommunication(EUARTandanX2speedimprovementmechanism.
ThefullystaticdesignoftheTS80C51Rx2allowstoreducesystempowerconsumptionbybringingtheclockfrequencydowntoanyvalue,evenDC,withoutlossofdata.
TheTS80C51Rx2has2software-selectablemodesofreducedactivityforfurtherreductioninpowerconsumption.IntheidlemodetheCPUisfrozenwhilethetimers,theserialportandtheinterruptsystemarestilloperating.Inthepower-downmodetheRAMissavedandallotherfunctionsareinoperative.
PDIL40PLCC44VQFP441.4TS80C51RA2TS80C51RD2TS83C51RB2TS83C51RC2TS83C51RD2TS87C51RB2TS87C51RC2TS87C51RD2
ROM(bytes
0016k32k64k000
EPROM(bytes
0000016k32k64k
XRAM(bytes
256768256256768256256768
TOTALRAM(bytes
512102451251210245125121024
I/O3232323232323232
PLCC68VQFP641.4TS80C51RD2TS83C51RD2TS87C51RD2
ROM(bytes
064k0
EPROM(bytes
0064k
XRAM(bytes
768768768
TOTALRAM(bytes
102410241024
I/O484848
2
AT/TS8xC51Rx2
4188E–8051–08/06

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AT/TS8xC51Rx2
3.BlockDiagram
D
D
c
s
I
AXxcsCCERxTVVEP2T2T(3(3
(1(1(1
(1XTAL1XTAL2EUART
RAMROM
XRAM256x8
0/16/32/64Kx8
/EPROM
256/768x8PCA
Timer2
ALE/PROG
C51
PSEN
CORE
IB-bus
CPU
EA/VPP
RD(3Timer0INTParallelI/OPorts&Ext.BusTimer1
Ctrl
WatchDog
WR
(3
Port0Port1Port2Port3Port4(2Port5
(2
(3(3(3(3
T
0
1
5
ET0
1
0
1
2
3
4
TTTPPPPPPSENNIIR(1:AlternatefunctionofPort1
(2:Onlyavailableonhighpincountpackages(3:AlternatefunctionofPort3
4188E–8051–08/06
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4.SFRMapping
TheSpecialFunctionRegisters(SFRsoftheTS80C51Rx2fallintothefollowingcategories:•C51coreregisters:ACC,B,DPH,DPL,PSW,SP,AUXR1•I/Oportregisters:P0,P1,P2,P3,P4,P5
•Timerregisters:T2CON,T2MOD,TCON,TH0,TH1,TH2,TMOD,TL0,TL1,TL2,RCAP2L,RCAP2H
•SerialI/Oportregisters:SADDR,SADEN,SBUF,SCON•Powerandclockcontrolregisters:PCON
•HDWWatchdogTimerReset:WDTRST,WDTPRG
•PCAregisters:CL,CH,CCAPiL,CCAPiH,CCON,CMOD,CCAPMi•Interruptsystemregisters:IE,IP,IPH•Others:AUXR,CKCON
4
AT/TS8xC51Rx2
4188E–8051–08/06

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AT/TS8xC51Rx2
Table4-1.
Bit
addressable0/8
F8h
B
00000000P5bit
addressable11111111
E0h
ACC
00000000CCON00X00000PSW
00000000T2CON00000000P4bit
addressable11111111
B8h
IPX000000P311111111IE00000000P211111111SCON00000000P111111111TCON00000000P0111111110/8
TMOD00000000SP
000001111/9
TL000000000DPL
000000002/A
TL100000000DPH
000000003/B
4/C
5/D
6/E
TH000000000
TH100000000
AUXR
XXXXXX00
CKCONXXXXXXX0PCON00X100007/F
SBUFXXXXXXXXSADDR00000000
AUXR1XXXX0XX0
WDTRSTXXXXXXXX
WDTPRGXXXXX000
SADEN00000000
IPH
X0000000
T2MODXXXXXX00
RCAP2L00000000
RCAP2H00000000
TL2
00000000
TH2
00000000
P5byteaddressable11111111
BFh
CMOD00XXX000
CCAPM0X0000000
CCAPM1X0000000
CCAPM2X0000000
CCAPM3X0000000
CCAPM4X0000000
CL00000000
CCAP0LXXXXXXXX
CCAP1LXXXXXXXX
CCAPL2LXXXXXXXX
CCAPL3LXXXXXXXX
CCAPL4LXXXXXXXX
NonBitaddressable1/9CH00000000
2/ACCAP0HXXXXXXXX
3/BCCAP1HXXXXXXXX
4/CCCAPL2HXXXXXXXX
5/DCCAPL3HXXXXXXXX
6/ECCAPL4HXXXXXXXX
7/F
FFh
AllSFRswiththeiraddressandtheirresetvalue
F0hF7h
E8hEFh
E7h
D8hDFh
D0hD7h
C8hCFh
C0hC7h
B0hB7h
A8hAFh
A0hA7h
98h9Fh
90h97h
88h8Fh
80h87h
reserved
5
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5.PinConfiguration
P1.0/T21P1.1/T2EX2
P1.23P1.34P1.45P1.56P1.67P1.78RST9P3.0/RxD10
PDIL/P3.1/TxD11
P3.2/INT012CDIL40P3.3/INT113P3.4/T014P3.5/T115P3.6/WR16P3.7/RD17XTAL218XTAL119VSS20
40VCC39P0.0/A038P0.1/A137P0.2/A236P0.3/A335P0.4/A434P0.5/A533P0.6/A632P0.7/A731EA/VPP30ALE/PROG29PSEN28P2.7/A1527P2.6/A1426P2.5/A1325P2.4/A1224P2.3/A1123P2.2/A1022P2.1/A921P2.0/A8
P1.5P1.6P1.7RSTP3.0/RxD
NIC*P3.1/TxDP3.2/INT0P3.3/INT1P3.4/T0P3.5/T1
7891011121314151617
P1.4P1.3P1.2P1.1/T2EXP1.0/T2VSS1/NIC*VCCP0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD36543214443424140
3938373635343332313029
P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7EA/VPPNIC*
ALE/PROGPSENP2.7/A15P2.6/A14P2.5/A13
PLCC/CQPJ44
1819202122232425262728P3.6/WRP3.7/RDXTAL2XTAL1VSSNIC*P2.0/A8P2.1/A93332313029282726252423
P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7EA/VPPNIC*
ALE/PROGPSENP2.7/A15P2.6/A14P2.5/A13
P2.2/A10P2.3/A11P2.4/A12
P1.5P1.6P1.7RSTP3.0/RxD
NIC*P3.1/TxDP3.2/INT0P3.3/INT1P3.4/T0P3.5/T11234567891011
1213141516171819202122P3.6/WRP3.7/RDXTAL2XTAL1VSSNIC*P2.0/A8P2.1/A9P2.2/A10P2.3/A11P2.4/A12
*NIC:NoInternalConnection
6
AT/TS8xC51Rx2
4188E–8051–08/06
P1.4P1.3P1.2P1.1/T2EXP1.0/T2VSS1/NIC*VCCP0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD34241403938373635344443
VQFP441.4

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4D5A/D6D7G
4.A/ADPOR51413/1
0456P.53P.5P
.0P
.CAAI/P.7V/CPI/ELNECAI/.7A/.62.1./05PN0PAENASPN2P2P5P5P
.2P
9876543216867666564636261
P5.51060P5.0P0.3/AD31159P2.4/A12P0.2/AD2
1258P2.3/A11P5.61357P4.7P0.1/AD11456P2.2/A10P0.0/AD0
1555P2.1/A9P5.71654P2.0/A8VCC17PLCC68
53
P4.6NIC1852NICP1.0/T21951VSSP4.02050P4.5P1.1/T2EX
2149XTAL1P1.22248XTAL2P1.32347P3.7/RDP4.12446P4.4P1.42545P3.6/WRP4.2
26
35363738394041424344
P4.3
27282930313233345.1P.617P.1TPSRCI
NCINCIN
DxDRCC/Ix00.NINCINCINT/T1T05.313P
.NN3I/IT//1P2.334P..T/33PPP
4G
D567OA/DR4..43.A/D5.A/DP6P.A/7/VP5/0ELN143/A1/A1AP5P5P0P0P.0PAEICN
AES7P.26P.2P.251/5P.5P.20P.5P
P0.3/AD3P5.516463626160595857565554535251504948P2.4/A12P0.2/AD2
247P2.3/A11P5.6346P4.7P0.1/AD1445P0.0/AD0
544P2.2/A10643P2.1/A9P2.0/A8VCCP5.7742841P4.6P1.0/T2VSS9VQFP641.4
40NIC1039VSSP1.1/T2EX
P4.01138P4.5P1.21237XTAL1P1.31336XTAL2P4.11435P3.7/RDP1.4
153416P3.6/WRP4.417181920212223242526272829303132
33P4.3
2.456.7TCCCC011
P.1P.1P1PSRINININDxC/RIIDxT0NTINT/T/0.NNT/1.I/2/345..3.NIC:NoInternalConnection
33P3P.3P3P
PP
4188E–8051–08/06
AT/TS8xC51Rx2
7

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PinNumber
MnemonicVSSVss1VCC
P0.0-P0.7
4039-32DIL20
LCC2214443-36
VQFP1.4
16393837-30
TypeIIII/O
NameAndFunctionGround:0Vreference
OptionalGround:ContacttheSalesOfficeforgroundconnection.
PowerSupply:Thisisthepowersupplyvoltagefornormal,idleandpower-downoperation
Port0:Port0isanopen-drain,bidirectionalI/Oport.Port0pinsthathave1swrittentothemfloatandcanbeusedashighimpedanceinputs.Port0pinsmustbepolarizedtoVccorVssinordertopreventanyparasiticcurrentconsumption.Port0isalsothemultiplexedlow-orderaddressanddatabusduringaccesstoexternalprogramanddatamemory.Inthisapplication,itusesstronginternalpull-upwhenemitting1s.Port0alsoinputsthecodebytesduringEPROMprogramming.Externalpull-upsarerequiredduringprogramverificationduringwhichP0outputsthecodebytes.
Port1:Port1isan8-bitbidirectionalI/Oportwithinternalpull-ups.Port1pinsthathave1swrittentothemarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallypulledlowwillsourcecurrentbecauseoftheinternalpull-ups.Port1alsoreceivesthelow-orderaddressbyteduringmemoryprogrammingandverification.AlternatefunctionsforPort1include:
12345678
P2.0-P2.7
21-28
2345678924-31
404142434445464718-25
I/OIII/OI/OI/OI/OI/OI/O
T2(P1.0:Timer/Counter2externalcountinput/ClockoutT2EX(P1.1:Timer/Counter2Reload/Capture/DirectionControlECI(P1.2:ExternalClockforthePCA
CEX0(P1.3:Capture/CompareExternalI/OforPCAmodule0CEX1(P1.4:Capture/CompareExternalI/OforPCAmodule1CEX0(P1.5:Capture/CompareExternalI/OforPCAmodule2CEX0(P1.6:Capture/CompareExternalI/OforPCAmodule3CEX0(P1.7:Capture/CompareExternalI/OforPCAmodule4
Port2:Port2isan8-bitbidirectionalI/Oportwithinternalpull-ups.Port2pinsthathave1swrittentothemarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallypulledlowwillsourcecurrentbecauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR.Inthisapplication,itusesstronginternalpull-ups
emitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@Ri,port2emitsthecontentsoftheP2SFR.SomePort2pins(P2.0toP2.5receivethehighorderaddressbitsduringEPROMprogrammingandverification:
Port3:Port3isan8-bitbidirectionalI/Oportwithinternalpull-ups.Port3pinsthathave1swrittentothemarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallypulledlowwillsourcecurrentbecauseoftheinternalpull-ups.SomePort3pins(P3.4toP3.5receivethehighorderaddressbitsduringEPROMprogrammingandverification.
Port3alsoservesthespecialfeaturesofthe80C51family,aslistedbelow.
1011
1113
57
IO
RXD(P3.0:SerialinputportTXD(P3.1:Serialoutputport
P1.0-P1.71-82-9
40-441-3
I/O
P3.0-P3.710-17
11,13-195,7-13
I/O
8
AT/TS8xC51Rx2
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AT/TS8xC51Rx2
PinNumber
Mnemonic
DIL121314151617
Reset
9
LCC14151617181910
VQFP1.4
89101112134
TypeIIIIOOI
NameAndFunction
INT0(P3.2:Externalinterrupt0INT1(P3.3:Externalinterrupt1T0(P3.4:Timer0externalinputT1(P3.5:Timer1externalinput
WR(P3.6:ExternaldatamemorywritestrobeRD(P3.7:Externaldatamemoryreadstrobe
Reset:Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunning,resetsthedevice.AninternaldiffusedresistortoVSSpermitsapower-onresetusingonlyanexternalcapacitortoVCC.Ifthehardwarewatchdogreachesitstime-out,theresetpinbecomesanoutputduringthetimetheinternalresetisactivated.
AddressLatchEnable/ProgramPulse:Outputpulseforlatchingthelowbyteoftheaddressduringanaccesstoexternalmemory.Innormaloperation,ALEisemittedataconstantrateof1/6(1/3inX2modetheoscillatorfrequency,andcanbeusedforexternaltimingorclocking.NotethatoneALEpulseisskippedduringeachaccesstoexternaldatamemory.Thispinisalsotheprogrampulseinput(PROGduringEPROMprogramming.ALEcanbedisabledbysettingSFR’sAUXR.0bit.Withthisbitset,ALEwillbeinactiveduringinternalfetches.
ProgramStoreENable:Thereadstrobetoexternalprogrammemory.Whenexecutingcodefromtheexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.PSENisnotactivatedduringfetchesfrominternalprogrammemory.
ExternalAccessEnable/ProgrammingSupplyVoltage:EAmustbeexternallyheldlowtoenablethedevicetofetchcodefromexternalprogrammemorylocations0000Hand3FFFH(RBor7FFFH(RC,orFFFFH(RD.IfEAisheldhigh,thedeviceexecutesfrominternalprogrammemoryunlesstheprogramcountercontainsanaddressgreaterthan3FFFH(RBor7FFFH(RCEAmustbeheldlowforROMlessdevices.Thispinalsoreceivesthe12.75Vprogrammingsupplyvoltage(VPPduringEPROMprogramming.Ifsecuritylevel1isprogrammed,EAwillbeinternallylatchedonReset.
Crystal1:Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockgeneratorcircuits.
Crystal2:Outputfromtheinvertingoscillatoramplifier
ALE/PROG303327O(I
PSEN293226O
EA/VPP
313529I
XTAL1192115I
XTAL2182014O
5.1PinDescriptionfor64/68pinPackages
Port4andPort5are8-bitbidirectionalI/Oportswithinternalpull-ups.Pinsthathave1swrittentothemarepulledhighbytheinternalpullupsandcanbeusedasinputs.
Asinputs,pinsthatareexternallypulledlowwillsourcecurrentbecauseoftheinternalpull-ups.Refertothepreviouspindescriptionforotherpins.Table5-1.
64/68PinPackagesConfiguration
Pin
VSSVCC
PLCC685117
SQUAREVQFP641.4
9/408
9
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P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7P2.0P2.1P2.2P2.3P2.4P2.5P2.6P2.7P3.0P3.1
151412119653192122232527282954555658596164653439
653264616059101213141618192043444547485053542528
Pin
P3.2P3.3P3.4P3.5P3.6P3.7RESETALE/PROG
PLCC684041424345473068
SQUAREVQFP641.4
2930313234362156
10
AT/TS8xC51Rx2
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AT/TS8xC51Rx2
PSENEA/VPPXTAL1XTAL2P4.0P4.1P4.2P4.3P4.4P4.5P4.6P4.7P5.0P5.1P5.2P5.3P5.4P5.5P5.6P5.7
6724948202426444650535760626378101316
5558383711151733353942464951526263147
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5.2TS80C51Rx2EnhancedFeatures
Incomparisontotheoriginal80C52,theTS8xC51Rx2implementssomenewfeatures,whichare:
•TheX2option.•TheDualDataPointer.•TheextendedRAM.
•TheProgrammableCounterArray(PCA.•TheWatchdog.
•The4levelinterruptprioritysystem.•Thepower-offflag.•TheONCEmode.•TheALEdisabling.
•SomeenhancedfeaturesarealsolocatedintheUARTandthetimer2.
5.3X2Feature
TheTS80C51Rx2coreneedsonly6clockperiodspermachinecycle.Thisfeaturecalled”X2”providesthefollowingadvantages:
•Dividesfrequencycrystalsby2(cheapercrystalswhilekeepingsameCPUpower.•SavespowerconsumptionwhilekeepingsameCPUpower(oscillatorpowersaving.•Savespowerconsumptionbydividingdynamicallyoperatingfrequencyby2inoperatingandidlemodes.
•IncreasesCPUpowerby2whilekeepingsamecrystalfrequency.
InordertokeeptheoriginalC51compatibility,adividerby2isinsertedbetweentheXTAL1sig-nalandthemainclockinputofthecore(phasegenerator.Thisdividermaybedisabledbysoftware.
5.3.1Description
TheclockforthewholecircuitandperipheralisfirstdividedbytwobeforebeingusedbytheCPUcoreandperipherals.ThisallowsanycyclicratiotobeacceptedonXTAL1input.InX2mode,asthisdividerisbypassed,thesignalsonXTAL1musthaveacyclicratiobetween40to60%.Figure5-1showstheclockgenerationblockdiagram.X2bitisvalidatedonXTAL1÷2ris-ingedgetoavoidglitcheswhenswitchingfromX2toSTDmode.Figure5-2showsthemodeswitchingwaveforms.
12
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AT/TS8xC51Rx2
Figure5-1.
ClockGenerationDiagram
XTAL1
FXTAL
2
XTAL1:2
01X2
statemachine:6clockcycles.CPUcontrol
FOSC
CKCONreg
Figure5-2.ModeSwitchingWaveforms
XTAL1
XTAL1:2
X2bit
CPUclock
STDMode
X2Mode
STDMode
TheX2bitintheCKCONregister(Table5-2allowstoswitchfrom12clockcyclesperinstruc-tionto6clockcyclesandviceversa.Atreset,thestandardspeedisactivated(STDmode.SettingthisbitactivatestheX2feature(X2mode.
Note:
InordertopreventanyincorrectoperationwhileoperatinginX2mode,usermustbeawarethatallperipheralsusingclockfrequencyastimereference(UART,timers,PCA...willhavetheirtimeref-erencedividedbytwo.Forexampleafreerunningtimergeneratinganinterruptevery20mswillthengenerateaninterruptevery10ms.UARTwith4800baudratewillhave9600baudrate.
Table5-2.
7-
CKCONRegister
CKCON-ClockControlRegister(8Fh
6-BitMnemonic
---5-4-3-2-1-0X2
BitNumber
765
Description
Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.
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BitNumber
4321
BitMnemonic
----
Description
Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.
CPUandperipheralclockbit
Cleartoselect12clockperiodspermachinecycle(STDmode,FOSC=FXTAL/2.Settoselect6clockperiodspermachinecycle(X2mode,FOSC=FXTAL.
0X2
ResetValue=XXXXXXX0bNotbitaddressable
ForfurtherdetailsontheX2feature,pleaserefertoANM072availableontheweb(http://www.atmel.com
14
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AT/TS8xC51Rx2
5.4
DualDataPointerRegister
Theadditionaldatapointercanbeusedtospeedupcodeexecutionandreducecodesizeinanumberofways.
ThedualDPTRstructureisawaybywhichthechipwillspecifytheaddressofanexternaldatamemorylocation.Therearetwo16-bitDPTRregistersthataddresstheexternalmemory,andasinglebitcalledDPS=AUXR1/bit0(Table5-3thatallowstheprogramcodetoswitchbetweenthem(RefertoFigure5-3.
Figure5-3.
UseofDualPointer

ExternalDataMemory
70DPS
DPTR1
DPTR0
AUXR1(A2H
DPH(83HDPL(82H
Table5-3.
AUXR1Address0A2H
AUXR1:AuxiliaryRegister1
-Resetvalue
X
-X
-X
-X
GF30
-X
-X
DPS0
Symbol
-DPS
Function
Notimplemented,reservedforfutureuse(1DataPointerSelection.
DPS01
OperatingModeDPTR0SelectedDPTR1Selected
GF3
Thisbitisageneralpurposeuserflag(2.
1.
Usersoftwareshouldnotwrite1storeservedbits.Thesebitsmaybeusedinfuture8051family
productstoinvokenewfeature.Inthatcase,theresetvalueofthenewbitwillbe0,anditsactivevaluewillbe1.Thevaluereadfromareservedbitisindeterminate.
GF3willnotbeavailableonfirstversionoftheRCdevices.
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6.Application
Softwarecantakeadvantageoftheadditionaldatapointerstobothincreasespeedandreducecodesize,forexample,blockoperations(copy,compare,search...arewellservedbyusingonedatapointerasa’source’pointerandtheotheroneasa"destination"pointer.ASSEMBLYLANGUAGE

;Blockmoveusingdualdatapointers;DestroysDPTR0,DPTR1,AandPSW
;note:DPSexitsoppositeofentrystate;unlessanextraINCAUXR1isadded;
00A2AUXR1EQU0A2H;
0000909000MOVDPTR,#SOURCE;addressofSOURCE000305A2INCAUXR1;switchdatapointers000590A000MOVDPTR,#DEST;addressofDEST0008LOOP:
000805A2INCAUXR1;switchdatapointers000AE0MOVXA,@DPTR;getabytefromSOURCE000BA3INCDPTR;incrementSOURCEaddress000C05A2INCAUXR1;switchdatapointers000EF0MOVX@DPTR,A;writethebytetoDEST000FA3INCDPTR;incrementDESTaddress001070F6JNZLOOP;checkfor0terminator001205A2INCAUXR1;(optionalrestoreDPS

INCisashort(2bytesandfast(12clockswaytomanipulatetheDPSbitintheAUXR1SFR.However,notethattheINCinstructiondoesnotdirectlyforcetheDPSbittoaparticularstate,butsimplytogglesit.Insimpleroutines,suchastheblockmoveexample,onlythefactthatDPSistoggledinthepropersequencematters,notitsactualvalue.Inotherwords,theblockmoveroutineworksthesamewhetherDPSis'0'or'1'onentry.Observethatwithoutthelastinstruc-tion(INCAUXR1,theroutinewillexitwithDPSintheoppositestate.
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AT/TS8xC51Rx2
6.1
ExpandedRAM(XRAM
TheTS80C51Rx2provideadditionalBytesoframdomaccessmemory(RAMspaceforincreaseddataparameterhandlingandhighlevellanguageusage.
RA2,RB2andRC2deviceshave256bytesofexpandedRAM,from00HtoFFHinexternaldataspace;RD2deviceshave768bytesofexpandedRAM,from00Hto2FFHinexternaldataspace.
TheTS80C51Rx2hasinternaldatamemorythatismappedintofourseparatesegments.Thefoursegmentsare:
•1.TheLower128bytesofRAM(addresses00Hto7FHaredirectlyandindirectlyaddressable.
•2.TheUpper128bytesofRAM(addresses80HtoFFHareindirectlyaddressableonly.•3.TheSpecialFunctionRegisters,SFRs,(addresses80HtoFFHaredirectlyaddressableonly.
•4.TheexpandedRAMbytesareindirectlyaccessedbyMOVXinstructions,andwiththeEXTRAMbitclearedintheAUXRregister.(SeeTable6-1.
TheLower128bytescanbeaccessedbyeitherdirectorindirectaddressing.TheUpper128bytescanbeaccessedbyindirectaddressingonly.TheUpper128bytesoccupythesameaddressspaceastheSFR.Thatmeanstheyhavethesameaddress,butarephysicallysepa-ratefromSFRspace.
Whenaninstructionaccessesaninternallocationaboveaddress7FH,theCPUknowswhethertheaccessistotheupper128bytesofdataRAMortoSFRspacebytheaddressingmodeusedintheinstruction.
•InstructionsthatusedirectaddressingaccessSFRspace.Forexample:MOV0A0H,#data,accessestheSFRatlocation0A0H(whichisP2.
•InstructionsthatuseindirectaddressingaccesstheUpper128bytesofdataRAM.Forexample:MOV@R0,#datawhereR0contains0A0H,accessesthedatabyteataddress0A0H,ratherthanP2(whoseaddressis0A0H.
•The256or768XRAMbytescanbeaccessedbyindirectaddressing,withEXTRAMbitclearedandMOVXinstructions.Thispartofmemorywhichisphysicallylocatedon-chip,logicallyoccupiesthefirst256or768bytesofexternaldatamemory.
•WithEXTRAM=0,theXRAMisindirectlyaddressed,usingtheMOVXinstructionin
combinationwithanyoftheregistersR0,R1oftheselectedbankorDPTR.AnaccesstoXRAMwillnotaffectportsP0,P2,P3.6(WRandP3.7(RD.Forexample,withEXTRAM=0,MOVX@R0,#datawhereR0contains0A0H,accessestheXRAMataddress0A0Hratherthanexternalmemory.AnaccesstoexternaldatamemorylocationshigherthanFFH(i.e.0100HtoFFFFH(higherthan2FFH(i.e.0300HtoFFFFHforRDdeviceswillbe
performedwiththeMOVXDPTRinstructionsinthesamewayasinthestandard80C51,sowithP0andP2asdata/addressbusses,andP3.6andP3.7aswriteandreadtimingsignals.RefertoFigure6-1.ForRDdevices,accessestoexpandedRAMfrom100Hto2FFHcanonlybedonethankstotheuseofDPTR.
•WithEXTRAM=1,MOVX@RiandMOVX@DPTRwillbesimilartothestandard80C51.MOVX@Riwillprovideaneight-bitaddressmultiplexedwithdataonPort0andanyoutputportpinscanbeusedtooutputhigherorderaddressbits.Thisistoprovidetheexternalpagingcapability.MOVX@DPTRwillgenerateasixteen-bitaddress.Port2outputsthehigh-ordereightaddressbits(thecontentsofDPHwhilePort0multiplexesthelow-ordereight
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addressbits(DPLwithdata.MOVX@RiandMOVX@DPTRwillgenerateeitherreadorwritesignalsonP3.6(WRandP3.7(RD.
Thestackpointer(SPmaybelocatedanywhereinthe256bytesRAM(lowerandupperRAMinternaldatamemory.ThestackmaynotbelocatedintheXRAM.
Figure6-1.
InternalandExternalDataMemoryAddress
FF
Upper128bytesInternal
Ram
indirectaccesses
XRAM256bytes
Lower128bytesInternalRam
directorindirectaccesses
00
0080
80FF
SpecialFunctionRegisterdirectaccesses
FFFF
FF(RA,RB,RC/2FF(RD
ExternalDataMemory
0100(RA,RB,RCor0300(RD
0000
Table6-1.
AuxiliaryRegisterAUXR
-X
-X
-X
-X
-X
-X
EXTRAM
0
AO0
AUXRAddress08EH
Resetvalue
Symbol
-AO
Function
Notimplemented,reservedforfutureuse.(1Disable/EnableALE
AO01
OperatingMode
ALEisemittedataconstantrateof1/6theoscillatorfrequency(or1/3ifX2modeisused
ALEisactiveonlyduringaMOVXorMOVCinstruction
EXTRAMInternal/ExternalRAM(00H-FFHaccessusingMOVX@Ri/@DPTREXTRAM
01
OperatingMode
InternalXRAMaccessusingMOVX@Ri/@DPTRExternaldatamemoryaccess
1.
Usersoftwareshouldnotwrite1storeservedbits.Thesebitsmaybeusedinfuture8051familyproductstoinvokenewfeatures.Inthatcase,theresetorinactivevalueofthenewbitwillbe0,anditsactivevaluewillbe1.Thevaluereadfromareservedbitisindeterminate.
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AT/TS8xC51Rx2
6.2
Timer2
Thetimer2intheTS80C51RX2iscompatiblewiththetimer2inthe80C52.
Itisa16-bittimer/counter:thecountismaintainedbytwoeight-bittimerregisters,TH2andTL2,connectedincascade.ItiscontrolledbyT2CONregister(SeeTable6-2andT2MODregister(SeeTable6-3.Timer2operationissimilartoTimer0andTimer1.C/T2selectsFOSC/12(timeroperationorexternalpinT2(counteroperationasthetimerclockinput.SettingTR2allowsTL2tobeincrementedbytheselectedinput.
Timer2has3operatingmodes:capture,autoreloadandBaudRateGenerator.ThesemodesareselectedbythecombinationofRCLK,TCLKandCP/RL2(T2CON,asdescribedintheAtmel8-bitMicrocontrollerHardwaredescription.
RefertotheAtmel8-bitMicrocontrollerHardwaredescriptionforthedescriptionofCaptureandBaudRateGeneratorModes.
InTS80C51RX2Timer2includesthefollowingenhancements:•Auto-reloadmodewithupordowncounter•Programmableclock-output
6.2.1
Auto-reloadMode
Theauto-reloadmodeconfigurestimer2asa16-bittimeroreventcounterwithautomaticreload.IfDCENbitinT2MODiscleared,timer2behavesasin80C52(refertotheAtmel8-bitMicrocontrollerHardwaredescription.IfDCENbitisset,timer2actsasanUp/downtimer/counterasshowninFigure6-2.InthismodetheT2EXpincontrolsthedirectionofcount.
WhenT2EXishigh,timer2countsup.TimeroverflowoccursatFFFFhwhichsetstheTF2flagandgeneratesaninterruptrequest.Theoverflowalsocausesthe16-bitvalueinRCAP2HandRCAP2LregisterstobeloadedintothetimerregistersTH2andTL2.
WhenT2EXislow,timer2countsdown.TimerunderflowoccurswhenthecountinthetimerregistersTH2andTL2equalsthevaluestoredinRCAP2HandRCAP2Lregisters.Theunder-flowsetsTF2flagandreloadsFFFFhintothetimerregisters.
TheEXF2bittoggleswhentimer2overflowsorunderflowsaccordingtothethedirectionofthecount.EXF2doesnotgenerateanyinterrupt.Thisbitcanbeusedtoprovide17-bitresolution.
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Figure6-2.Auto-reloadModeUp/DownCounter(DCEN=1
(:6inX2mode
:12
FXTAL
FOSC
T2
C/T2T2CONreg
TR2T2CONreg
XTAL1
01
T2EX:
(DOWNCOUNTINGRELOADVALUE
FFhFFh(8-bit(8-bit
ifDCEN=1,1=UPifDCEN=1,0=DOWNifDCEN=0,up
counting
T2CONregTOGGLE
EXF2
TL2
(8-bit
TH2(8-bit
TF2T2CONreg
TIMER2INTERRUPT
RCAP2L(8-bitRCAP2H(8-bit
(UPCOUNTINGRELOADVALUE
6.2.2
ProgrammableClock-Output
Intheclock-outmode,timer2operatesasa50%-duty-cycle,programmableclockgenerator(SeeFigure6-3.TheinputclockincrementsTL2atfrequencyFOSC/2.Thetimerrepeatedlycountstooverflowfromaloadedvalue.Atoverflow,thecontentsofRCAP2HandRCAP2Lreg-istersareloadedintoTH2andTL2.Inthismode,timer2overflowsdonotgenerateinterrupts.Theformulagivestheclock-outfrequencyasafunctionofthesystemoscillatorfrequencyandthevalueintheRCAP2HandRCAP2Lregisters:
Fosc
Clock–OutFrequency=----------------------------------------------------------------------------------------4×(65536–RCAP2H⁄RCAP2L
Fora16MHzsystemclock,timer2hasaprogrammablefrequencyrangeof61Hz(FOSC/216to4MHz(FOSC/4.ThegeneratedclocksignalisbroughtouttoT2pin(P1.0.Timer2isprogrammedfortheclock-outmodeasfollows:•SetT2OEbitinT2MODregister.•ClearC/T2bitinT2CONregister.
•Determinethe16-bitreloadvaluefromtheformulaandenteritinRCAP2H/RCAP2Lregisters.
•Entera16-bitinitialvalueintimerregistersTH2/TL2.Itcanbethesameasthereloadvalueoradifferentonedependingontheapplication.
•Tostartthetimer,setTR2runcontrolbitinT2CONregister.
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AT/TS8xC51Rx2
Itispossibletousetimer2asabaudrategeneratorandaclockgeneratorsimultaneously.Forthisconfiguration,thebaudratesandclockfrequenciesarenotindependentsincebothfunc-tionsusethevaluesintheRCAP2HandRCAP2Lregisters.
Figure6-3.
Clock-OutModeC/T2=0
XTAL1
:2(:1inX2mode
TR2T2CONreg
TL2(8-bit
TH2(8-bit
OVERFLOW
RCAP2L(8-bit
Toggle
T2
Q
D
RCAP2H(8-bit
T2OET2MODreg
T2EX
EXEN2T2CONreg
EXF2T2CONreg
TIMER2INTERRUPT
Table6-2.
7TF2
T2CONRegister
T2CON-Timer2ControlRegister(C8h
6EXF2
5RCLK
4TCLK
3EXEN2
2TR2
1C/T2#
0CP/RL2#
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BitNumber
7
Bit
MnemonicDescription
TF2
Timer2overflowFlag
Mustbeclearedbysoftware.
Setbyhardwareontimer2overflow,ifRCLK=0andTCLK=0.
Timer2ExternalFlag
SetwhenacaptureorareloadiscausedbyanegativetransitiononT2EXpinifEXEN2=1.
Whenset,causestheCPUtovectortotimer2interruptroutinewhentimer2interruptisenabled.
Mustbeclearedbysoftware.EXF2doesn’tcauseaninterruptinUp/downcountermode(DCEN=1
ReceiveClockbit
Cleartousetimer1overflowasreceiveclockforserialportinmode1or3.Settousetimer2overflowasreceiveclockforserialportinmode1or3.TransmitClockbit
Cleartousetimer1overflowastransmitclockforserialportinmode1or3.Settousetimer2overflowastransmitclockforserialportinmode1or3.
Timer2ExternalEnablebit
CleartoignoreeventsonT2EXpinfortimer2operation.
SettocauseacaptureorreloadwhenanegativetransitiononT2EXpinisdetected,iftimer2isnotusedtoclocktheserialport.Timer2RuncontrolbitCleartoturnofftimer2.Settoturnontimer2.
Timer/Counter2selectbit
Clearfortimeroperation(inputfrominternalclocksystem:FOSC.
Setforcounteroperation(inputfromT2inputpin,fallingedgetrigger.Mustbe0forclockoutmode.
Timer2Capture/Reloadbit
IfRCLK=1orTCLK=1,CP/RL2#isignoredandtimerisforcedtoauto-reloadontimer2overflow.
Cleartoauto-reloadontimer2overflowsornegativetransitionsonT2EXpinifEXEN2=1.SettocaptureonnegativetransitionsonT2EXpinifEXEN2=1.
6EXF2
5RCLK
4TCLK
3EXEN2
2TR2
1C/T2#
0CP/RL2#
ResetValue=00000000bBitaddressable
Table6-3.
7-
T2MODRegister
T2MOD-Timer2ModeControlRegister(C9h
6-5-4-3-2-1T2OE
0DCEN
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AT/TS8xC51Rx2
BitNumber
765432
BitMnemonic
------Description
Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Timer2OutputEnablebit
CleartoprogramP1.0/T2asclockinputorI/Oport.SettoprogramP1.0/T2asclockoutput.DownCounterEnablebit
Cleartodisabletimer2asup/downcounter.Settoenabletimer2asup/downcounter.
1T2OE
0DCEN
ResetValue=XXXXXX00bNotbitaddressable
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6.3ProgrammableCounterArrayPCA
ThePCAprovidesmoretimingcapabilitieswithlessCPUinterventionthanthestandardtimer/counters.Itsadvantagesincludereducedsoftwareoverheadandimprovedaccuracy.ThePCAconsistsofadedicatedtimer/counterwhichservesasthetimebaseforanarrayoffivecompare/capturemodules.Itsclockinputcanbeprogrammedtocountanyoneofthefollowingsignals:
•Oscillatorfrequency÷12(÷6inX2mode•Oscillatorfrequency÷4(÷2inX2mode•Timer0overflow
•ExternalinputonECI(P1.2
Eachcompare/capturemodulescanbeprogrammedinanyoneofthefollowingmodes:•risingand/orfallingedgecapture,•softwaretimer,•high-speedoutput,or•pulsewidthmodulator.
Module4canalsobeprogrammedasawatchdogtimer(SeeSection"PCAWatchdogTimer",page33.
Whenthecompare/capturemodulesareprogrammedinthecapturemode,softwaretimer,orhighspeedoutputmode,aninterruptcanbegeneratedwhenthemoduleexecutesitsfunction.AllfivemodulesplusthePCAtimeroverflowshareoneinterruptvector.
ThePCAtimer/counterandcompare/capturemodulessharePort1forexternalI/O.Thesepinsarelistedbelow.IftheportisnotusedforthePCA,itcanstillbeusedforstandardI/O.
PCAcomponent16-bitCounter16-bitModule016-bitModule116-bitModule216-bitModule316-bitModule4
ExternalI/OPinP1.2/ECIP1.3/CEX0P1.4/CEX1P1.5/CEX2P1.6/CEX3P1.7/CEX4
ThePCAtimerisacommontimebaseforallfivemodules(SeeFigure6-4.ThetimercountsourceisdeterminedfromtheCPS1andCPS0bitsintheCMODSFR(SeeTable6-4andcanbeprogrammedtorunat:
•1/12theoscillatorfrequency.(Or1/6inX2Mode•1/4theoscillatorfrequency.(Or1/2inX2Mode•TheTimer0overflow
•TheinputontheECIpin(P1.2
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AT/TS8xC51Rx2
Figure6-4.
PCATimer/Counter
ToPCAmodules
Fosc/12Fosc/4T0OVFP1.2
overflow
CH
CL
16bitup/downcounter
It
CIDL
Idle
WDTECPS1CPS0ECF
CMOD0xD9

CFCRCCF4CCF3CCF2CCF1CCF0
CCON0xD8
Table6-4.CMOD:PCACounterModeRegister
CIDL0
WDTE0
-X
-X
-X
CPS10
CPS00
ECF0
CMODAddress0D9H
Resetvalue
SymbolCIDLWDTE-CPS1CPS0
Function
CounterIdlecontrol:CIDL=0programsthePCACountertocontinuefunctioningduringidleMode.CIDL=1programsittobegatedoffduringidle.
WatchdogTimerEnable:WDTE=0disablesWatchdogTimerfunctiononPCAModule4.WDTE=1enablesit.
Notimplemented,reservedforfutureuse.(1PCACountPulseSelectbit1.PCACountPulseSelectbit0.CPS10011
CPS00101
SelectedPCAinput.(2
Internalclockfosc/12(Orfosc/6inX2Mode.Internalclockfosc/4(Orfosc/2inX2Mode.Timer0Overflow
ExternalclockatECI/P1.2pin(maxrate=fosc/8
ECF
PCAEnableCounterOverflowinterrupt:ECF=1enablesCFbitinCCONtogenerateaninterrupt.ECF=0disablesthatfunctionofCF.
1.
Usersoftwareshouldnotwrite1storeservedbits.Thesebitsmaybeusedinfuture8051familyproductstoinvokenewfeatures.Inthatcase,theresetorinactivevalueofthenewbitwillbe0,anditsactivevaluewillbe1.Thevaluereadfromareservedbitisindeterminate.fosc=oscillatorfrequency
2.
TheCMODSFRincludesthreeadditionalbitsassociatedwiththePCA(SeeFigure6-4andTable6-4.
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•TheCIDLbitwhichallowsthePCAtostopduringidlemode.
•TheWDTEbitwhichenablesordisablesthewatchdogfunctiononmodule4.
•TheECFbitwhichwhensetcausesaninterruptandthePCAoverflowflagCF(intheCCONSFRtobesetwhenthePCAtimeroverflows.
TheCCONSFRcontainstheruncontrolbitforthePCAandtheflagsforthePCAtimer(CFandeachmodule(RefertoTable6-5.
•BitCR(CCON.6mustbesetbysoftwaretorunthePCA.ThePCAisshutoffbyclearingthisbit.
•BitCF:TheCFbit(CCON.7issetwhenthePCAcounteroverflowsandaninterruptwillbegeneratediftheECFbitintheCMODregisterisset.TheCFbitcanonlybeclearedbysoftware.
•Bits0through4aretheflagsforthemodules(bit0formodule0,bit1formodule1,etc.andaresetbyhardwarewheneitheramatchoracaptureoccurs.Theseflagsalsocanonlybeclearedbysoftware.

Table6-5.CCON:PCACounterControlRegister
CF0
CR0
-X
CCF40
CCF30
CCF20
CCF10
CCF00
CCONAddress0D8H
Resetvalue
SymbolCF
Function
PCACounterOverflowflag.Setbyhardwarewhenthecounterrollsover.CFflags
aninterruptifbitECFinCMODisset.CFmaybesetbyeitherhardwareorsoftwarebutcanonlybeclearedbysoftware.
PCACounterRuncontrolbit.SetbysoftwaretoturnthePCAcounteron.MustbeclearedbysoftwaretoturnthePCAcounteroff.Notimplemented,reservedforfutureuse.(1
PCAModule4interruptflag.Setbyhardwarewhenamatchorcaptureoccurs.Mustbeclearedbysoftware.
PCAModule3interruptflag.Setbyhardwarewhenamatchorcaptureoccurs.Mustbeclearedbysoftware.
PCAModule2interruptflag.Setbyhardwarewhenamatchorcaptureoccurs.Mustbeclearedbysoftware.
PCAModule1interruptflag.Setbyhardwarewhenamatchorcaptureoccurs.Mustbeclearedbysoftware.
PCAModule0interruptflag.Setbyhardwarewhenamatchorcaptureoccurs.Mustbeclearedbysoftware.
CR-CCF4CCF3CCF2CCF1CCF0
1.
Usersoftwareshouldnotwrite1storeservedbits.Thesebitsmaybeusedinfuture8051familyproductstoinvokenewfeatures.Inthatcase,theresetorinactivevalueofthenewbitwillbe0,anditsactivevaluewillbe1.Thevaluereadfromareservedbitisindeterminate.
Thewatchdogtimerfunctionisimplementedinmodule4(SeeFigure6-7.ThePCAinterruptsystemisshowninFigure6-5.
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AT/TS8xC51Rx2
Figure6-5.
PCAInterruptSystem
CF
PCATimer/Counter
CR
CCF4CCF3CCF2CCF1CCF0
CCON0xD8
Module0Module1Module2Module3Module4
CMOD.0
ECF
ECCFnCCAPMn.0
IE.6EC
IE.7EA
ToInterruptprioritydecoder
PCAModules:eachoneofthefivecompare/capturemoduleshassixpossiblefunctions.Itcanperform:
•16-bitCapture,positive-edgetriggered,•16-bitCapture,negative-edgetriggered,
•16-bitCapture,bothpositiveandnegative-edgetriggered,•16-bitSoftwareTimer,•16-bitHighSpeedOutput,•8-bitPulseWidthModulator.
Inaddition,module4canbeusedasaWatchdogTimer.
EachmoduleinthePCAhasaspecialfunctionregisterassociatedwithit.Theseregistersare:CCAPM0formodule0,CCAPM1formodule1,etc.(SeeTable6-6.Theregisterscontainthebitsthatcontrolthemodethateachmodulewilloperatein.
•TheECCFbit(CCAPMn.0wheren=0,1,2,3,or4dependingonthemoduleenablestheCCFflagintheCCONSFRtogenerateaninterruptwhenamatchorcompareoccursintheassociatedmodule.
•PWM(CCAPMn.1enablesthepulsewidthmodulationmode.
•TheTOGbit(CCAPMn.2whensetcausestheCEXoutputassociatedwiththemoduletotogglewhenthereisamatchbetweenthePCAcounterandthemodule'scapture/compareregister.
•ThematchbitMAT(CCAPMn.3whensetwillcausetheCCFnbitintheCCONregistertobesetwhenthereisamatchbetweenthePCAcounterandthemodule'scapture/compareregister.
•ThenexttwobitsCAPN(CCAPMn.4andCAPP(CCAPMn.5determinetheedgethatacaptureinputwillbeactiveon.TheCAPNbitenablesthenegativeedge,andtheCAPPbitenablesthepositiveedge.Ifbothbitsaresetbothedgeswillbeenabledandacapturewilloccurforeithertransition.
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•ThelastbitintheregisterECOM(CCAPMn.6whensetenablesthecomparatorfunction.
Table6-7showstheCCAPMnsettingsforthevariousPCAfunctions.
.
Table6-6.

CCAPMn:PCAModulesCompare/CaptureControlRegisters
CCAPM0=0DAH
CCAPM1=0DBHCCAPM2=0DCHCCAPM3=0DDHCCAPM4=0DEH
-Resetvalue
X

CCAPMnAddress
n=0-4
ECOMnCAPPn
0
0
CAPNn0
MATn0
TOGn0
PWMm0
ECCFn0
Symbol-ECOMnCAPPnCAPNnMATnTOGnPWMnECCFn
Function
Notimplemented,reservedforfutureuse.(1
EnableComparator.ECOMn=1enablesthecomparatorfunction.CapturePositive,CAPPn=1enablespositiveedgecapture.CaptureNegative,CAPNn=1enablesnegativeedgecapture.
Match.WhenMATn=1,amatchofthePCAcounterwiththismodule'scompare/captureregistercausestheCCFnbitinCCONtobeset,flagginganinterrupt.
Toggle.WhenTOGn=1,amatchofthePCAcounterwiththismodule'scompare/captureregistercausestheCEXnpintotoggle.
PulseWidthModulationMode.PWMn=1enablestheCEXnpintobeusedasapulsewidthmodulatedoutput.
EnableCCFinterrupt.Enablescompare/captureflagCCFnintheCCONregistertogenerateaninterrupt.
1.
Usersoftwareshouldnotwrite1storeservedbits.Thesebitsmaybeusedinfuture8051familyproductstoinvokenewfeatures.Inthatcase,theresetorinactivevalueofthenewbitwillbe0,anditsactivevaluewillbe1.Thevaluereadfromareservedbitisindeterminate.
Table6-7.
ECOMn
0XXX1111
PCAModuleModes(CCAPMnRegisters
CAPNn00110000
MATn00001101
TOGn0000010X
PWMm00000010
ECCFn0XXXXX0X
ModuleFunctionNoOperation
16-bitcapturebyapositive-edgetriggeronCEXn
16-bitcapturebyanegativetriggeronCEXn
16-bitcapturebyatransitiononCEXn16-bitSoftwareTimer/Comparemode.16-bitHighSpeedOutput8-bitPWM
WatchdogTimer(module4only
CAPPn01010000
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AT/TS8xC51Rx2
TherearetwoadditionalregistersassociatedwitheachofthePCAmodules.TheyareCCAPnHandCCAPnLandthesearetheregistersthatstorethe16-bitcountwhenacaptureoccursoracompareshouldoccur.WhenamoduleisusedinthePWMmodetheseregistersareusedtocontrolthedutycycleoftheoutput(SeeTable6-8&Table6-9

Table6-8.CCAPnH:PCAModulesCapture/CompareRegistersHigh
CCAP0H=0FAHCCAP1H=0FBHCCAP2H=0FCH
CCAP3H=0FDHCCAP4H=0FEH
7
Resetvalue
0
60
50
40
30
20
10
00
CCAPnHAddress
n=0-4
Table6-9.CCAPnL:PCAModulesCapture/CompareRegistersLow
CCAP0L=0EAHCCAP1L=0EBHCCAP2L=0ECHCCAP3L=0EDHCCAP4L=0EEH
7
Resetvalue
0
60
50
40
30
20
10
00
CCAPnLAddress
n=0-4
Table6-10.
CH
Address0F9H
CH:PCACounterHigh
7
Resetvalue
0
60
50
40
30
20
10
00
Table6-11.
CL
Address0E9H
CL:PCACounterLow
7
Resetvalue
0
60
50
40
30
20
10
00
6.3.1
PCACaptureMode
TouseoneofthePCAmodulesinthecapturemodeeitheroneorbothoftheCCAPMbitsCAPNandCAPPforthatmodulemustbeset.TheexternalCEXinputforthemodule(onport1issampledforatransition.WhenavalidtransitionoccursthePCAhardwareloadsthevalueofthePCAcounterregisters(CHandCLintothemodule'scaptureregisters(CCAPnLandCCAPnH.IftheCCFnbitforthemoduleintheCCONSFRandtheECCFnbitintheCCAPMnSFRaresetthenaninterruptwillbegenerated(RefertoFigure6-6.
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Figure6-6.PCACaptureMode
CF
CR
CCF4CCF3CCF2CCF1CCF0CCON
0xD8
PCAIT
PCACounter/Timer
Cex.n
Capture
CHCL
CCAPnHCCAPnL
ECOMnCAPPnCAPNnMATnTOGnPWMnECCFnCCAPMn,n=0to4
0xDAto0xDE

6.3.2
16-bitSoftwareTimer/CompareMode
ThePCAmodulescanbeusedassoftwaretimersbysettingboththeECOMandMATbitsinthemodulesCCAPMnregister.ThePCAtimerwillbecomparedtothemodule'scaptureregis-tersandwhenamatchoccursaninterruptwilloccuriftheCCFn(CCONSFRandtheECCFn(CCAPMnSFRbitsforthemodulearebothset(SeeFigure6-7.
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Figure6-7.
PCACompareModeandPCAWatchdogTimer
CCON
CF
WritetoCCAPnL
WritetoCCAPnH
1
0
Enable
16bitcomparator
RESET*
Reset
PCAIT
CCAPnH
CCAPnL
Match
CR
CCF4CCF3CCF2CCF1CCF0
0xD8
CHCL
PCAcounter/timer
ECOMnCAPPnCAPNnMATnTOGnPWMnECCFn
CCAPMn,n=0to40xDAto0xDE
CIDLWDTECPS1CPS0ECF
CMOD0xD9
*OnlyforModule4
BeforeenablingECOMbit,CCAPnLandCCAPnHshouldbesetwithanonzerovalue,other-wiseanunwantedmatchcouldhappen.WritingtoCCAPnHwillsettheECOMbit.
OnceECOMset,writingCCAPnLwillclearECOMsothatanunwantedmatchdoesn’toccurwhilemodifyingthecomparevalue.WritingtoCCAPnHwillsetECOM.Forthisreason,usersoftwareshouldwriteCCAPnLfirst,andthenCCAPnH.Ofcourse,theECOMbitcanstillbecontrolledbyaccessingtoCCAPMnregister.
6.3.3
HighSpeedOutputMode
InthismodetheCEXoutput(onport1associatedwiththePCAmodulewilltoggleeachtimeamatchoccursbetweenthePCAcounterandthemodule'scaptureregisters.ToactivatethismodetheTOG,MAT,andECOMbitsinthemodule'sCCAPMnSFRmustbeset(SeeFigure6-8.
ApriorwritemustbedonetoCCAPnLandCCAPnHbeforewritingtheECOMnbit.
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Figure6-8.PCAHighSpeedOutputMode
CF
CR
CCF4CCF3CCF2CCF1CCF0
CCON0xD8
Writeto
CCAPnLReset
WritetoCCAPnH
1
0
Enable
16bitcomparator
PCAIT
CCAPnH
CCAPnL
Match
CHCL
CEXn
PCAcounter/timer
CCAPMn,n=0to40xDAto0xDE
ECOMnCAPPnCAPNnMATnTOGnPWMnECCFn
BeforeenablingECOMbit,CCAPnLandCCAPnHshouldbesetwithanonzerovalue,other-wiseanunwantedmatchcouldhappen.
OnceECOMset,writingCCAPnLwillclearECOMsothatanunwantedmatchdoesn’toccurwhilemodifyingthecomparevalue.WritingtoCCAPnHwillsetECOM.Forthisreason,usersoftwareshouldwriteCCAPnLfirst,andthenCCAPnH.Ofcourse,theECOMbitcanstillbecontrolledbyaccessingtoCCAPMnregister.
6.3.4
PulseWidthModulatorMode
AllofthePCAmodulescanbeusedasPWMoutputs.Figure6-9showsthePWMfunction.ThefrequencyoftheoutputdependsonthesourceforthePCAtimer.AllofthemoduleswillhavethesamefrequencyofoutputbecausetheyallsharethePCAtimer.Thedutycycleofeachmoduleisindependentlyvariableusingthemodule'scaptureregisterCCAPLn.WhenthevalueofthePCACLSFRislessthanthevalueinthemodule'sCCAPLnSFRtheoutputwillbelow,whenitisequaltoorgreaterthantheoutputwillbehigh.WhenCLoverflowsfromFFto00,CCAPLnisreloadedwiththevalueinCCAPHn.ThisallowsupdatingthePWMwithoutglitches.ThePWMandECOMbitsinthemodule'sCCAPMnregistermustbesettoenablethePWMmode.
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Figure6-9.
PCAPWMMode
CCAPnH
Overflow
CCAPnL
“0”
Enable
8bitcomparator
<Š
“1”
CEXn
CL
PCAcounter/timer
ECOMnCAPPnCAPNnMATnTOGnPWMnECCFnCCAPMn,n=0to40xDAto0xDE
6.3.5
PCAWatchdogTimer
Anon-boardwatchdogtimerisavailablewiththePCAtoimprovethereliabilityofthesystemwithoutincreasingchipcount.Watchdogtimersareusefulforsystemsthataresusceptibletonoise,powerglitches,orelectrostaticdischarge.Module4istheonlyPCAmodulethatcanbeprogrammedasawatchdog.However,thismodulecanstillbeusedforothermodesifthewatchdogisnotneeded.Figure6-7showsadiagramofhowthewatchdogworks.Theuserpre-loadsa16-bitvalueinthecompareregisters.Justliketheothercomparemodes,this16-bitvalueiscomparedtothePCAtimervalue.Ifamatchisallowedtooccur,aninternalresetwillbegenerated.ThiswillnotcausetheRSTpintobedrivenhigh.
Inordertoholdoffthereset,theuserhasthreeoptions:
•1.PeriodicallychangethecomparevaluesoitwillnevermatchthePCAtimer,
•2.periodicallychangethePCAtimervaluesoitwillnevermatchthecomparevalues,or•3.DisablethewatchdogbyclearingtheWDTEbitbeforeamatchoccursandthenre-enableit.
Thefirsttwooptionsaremorereliablebecausethewatchdogtimerisneverdisabledasinoption#3.Iftheprogramcounterevergoesastray,amatchwilleventuallyoccurandcauseaninternalreset.ThesecondoptionisalsonotrecommendedifotherPCAmodulesarebeingused.Remember,thePCAtimeristhetimebaseforallmodules;changingthetimebaseforothermoduleswouldnotbeagoodidea.Thus,inmostapplicationsthefirstsolutionisthebestoption.Thiswatchdogtimerwon’tgeneratearesetoutontheresetpin.
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6.4TS80C51Rx2SerialI/OPort
TheserialI/OportintheTS80C51Rx2iscompatiblewiththeserialI/Oportinthe80C52.Itprovidesbothsynchronousandasynchronouscommunicationmodes.ItoperatesasanUni-versalAsynchronousReceiverandTransmitter(UARTinthreefull-duplexmodes(Modes1,2and3.Asynchronoustransmissionandreceptioncanoccursimultaneouslyandatdifferentbaudrates
SerialI/Oportincludesthefollowingenhancements:•Framingerrordetection•Automaticaddressrecognition
6.4.1
FramingErrorDetection
Framingbiterrordetectionisprovidedforthethreeasynchronousmodes(modes1,2and3.Toenabletheframingbiterrordetectionfeature,setSMOD0bitinPCONregister(SeeFigure6-10.
Figure6-10.FramingErrorBlockDiagram
SM0/FESM1
SM2
REN
TB8
RB8
TI
RI
SCON(98h
SetFEbitifstopbitis0(framingerror(SMOD0=1SM0toUARTmodecontrol(SMOD=0
SMOD1SMOD0
-POF
GF1
GF0
PD
IDL
PCON(87h
ToUARTframingerrorcontrol
Whenthisfeatureisenabled,thereceivercheckseachincomingdataframeforavalidstopbit.AninvalidstopbitmayresultfromnoiseontheseriallinesorfromsimultaneoustransmissionbytwoCPUs.Ifavalidstopbitisnotfound,theFramingErrorbit(FEinSCONregister(SeeTable6-14.bitisset.
SoftwaremayexamineFEbitaftereachreceptiontocheckfordataerrors.Onceset,onlysoft-wareoraresetcanclearFEbit.SubsequentlyreceivedframeswithvalidstopbitscannotclearFEbit.WhenFEfeatureisenabled,RIrisesonstopbitinsteadofthelastdatabit(SeeFigure6-11andFigure6-12.
Figure6-11.UARTTimingsinMode1
RXD
Startbit
RI
SMOD0=XFE
SMOD0=1
D0
D1
D2
D3
D4
D5
D6
D7
Stopbit
Databyte
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Figure6-12.UARTTimingsinModes2and3
RXD
Startbit
RI
SMOD0=0RI
SMOD0=1FE
SMOD0=1
D0
D1
D2
D3
D4
D5
D6
D7
D8NinthStopbitbit
Databyte
6.4.2
AutomaticAddressRecognition
Theautomaticaddressrecognitionfeatureisenabledwhenthemultiprocessorcommunicationfeatureisenabled(SM2bitinSCONregisterisset.
Implementedinhardware,automaticaddressrecognitionenhancesthemultiprocessorcommu-nicationfeaturebyallowingtheserialporttoexaminetheaddressofeachincomingcommandframe.Onlywhentheserialportrecognizesitsownaddress,thereceiversetsRIbitinSCONregistertogenerateaninterrupt.ThisensuresthattheCPUisnotinterruptedbycommandframesaddressedtootherdevices.
Ifdesired,youmayenabletheautomaticaddressrecognitionfeatureinmode1.Inthisconfigu-ration,thestopbittakestheplaceoftheninthdatabit.BitRIissetonlywhenthereceivedcommandframeaddressmatchesthedevice’saddressandisterminatedbyavalidstopbit.Tosupportautomaticaddressrecognition,adeviceisidentifiedbyagivenaddressandabroad-castaddress.
Note:
Themultiprocessorcommunicationandautomaticaddressrecognitionfeaturescannotbeenabledinmode0(i.e.settingSM2bitinSCONregisterinmode0hasnoeffect.
6.4.3
GivenAddress
EachdevicehasanindividualaddressthatisspecifiedinSADDRregister;theSADENregisterisamaskbytethatcontainsdon’t-carebits(definedbyzerostoformthedevice’sgivenaddress.Thedon’t-carebitsprovidetheflexibilitytoaddressoneormoreslavesatatime.Thefollowingexampleillustrateshowagivenaddressisformed.
Toaddressadevicebyitsindividualaddress,theSADENmaskbytemustbe11111111b.
Forexample:
SADDR01010110bSADEN11111100bGiven010101XXb
Thefollowingisanexampleofhowtousegivenaddressestoaddressdifferentslaves:
SlaveA:SADDR11110001b
SADEN11111010b
Given11110X0XbSlaveB:SADDR11110011b
SADEN11111001b
Given11110XX1b
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SlaveC:SADDR11110010b
SADEN11111101b
Given111100X1b
TheSADENbyteisselectedsothateachslavemaybeaddressedseparately.
ForslaveA,bit0(theLSBisadon’t-carebit;forslavesBandC,bit0isa1.TocommunicatewithslaveAonly,themastermustsendanaddresswherebit0isclear(e.g.11110000b.ForslaveA,bit1isa1;forslavesBandC,bit1isadon’tcarebit.TocommunicatewithslavesBandC,butnotslaveA,themastermustsendanaddresswithbits0and1bothset(e.g.11110011b.
TocommunicatewithslavesA,BandC,themastermustsendanaddresswithbit0set,bit1clear,andbit2clear(e.g.11110001b.
6.4.4
BroadcastAddress
AbroadcastaddressisformedfromthelogicalORoftheSADDRandSADENregisterswithzerosdefinedasdon’t-carebits,e.g.:
SADDR01010110bSADEN11111100b
Broadcast=SADDRORSADEN1111111Xb
Theuseofdon’t-carebitsprovidesflexibilityindefiningthebroadcastaddress,howeverinmostapplications,abroadcastaddressisFFh.Thefollowingisanexampleofusingbroadcastaddresses:
SlaveA:SADDR11110001b
SADEN11111010b
Broadcast11111X11b,SlaveB:SADDR11110011b
SADEN11111001b
Broadcast11111X11B,SlaveC:SADDR=11110010b
SADEN11111101b
Broadcast11111111b
ForslavesAandB,bit2isadon’tcarebit;forslaveC,bit2isset.Tocommunicatewithalloftheslaves,themastermustsendanaddressFFh.TocommunicatewithslavesAandB,butnotslaveC,themastercansendandaddressFBh.
6.4.5
ResetAddresses
Onreset,theSADDRandSADENregistersareinitializedto00h,i.e.thegivenandbroadcastaddressesareXXXXXXXXb(alldon’t-carebits.Thisensuresthattheserialportwillreplytoanyaddress,andso,thatitisbackwardscompatiblewiththe80C51microcontrollersthatdonotsupportautomaticaddressrecognition.
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Table6-12.
7
SADEN-SlaveAddressMaskRegister(B9h
6
5
4
3
2
1
0
ResetValue=00000000bNotbitaddressable
Table6-13.
7
SADDR-SlaveAddressRegister(A9h
6
5
4
3
2
1
0
ResetValue=00000000bNotbitaddressable
Table6-14.
7FE/SM0
SCONRegister
SCON-SerialControlRegister(98h
6SM1
5SM2
4REN
3TB8
2RB8
1TI
0RI
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BitNumber
BitMnemonic
Description
FramingErrorbit(SMOD0=1
Cleartoresettheerrorstate,notclearedbyavalidstopbit.Setbyhardwarewhenaninvalidstopbitisdetected.SMOD0mustbesettoenableaccesstotheFEbitSerialportModebit0
RefertoSM1forserialportmodeselection.
SMOD0mustbeclearedtoenableaccesstotheSM0bitSerialportModebit1
SM0SM1ModeDescriptionBaudRate
7FE
SM0
6SM1
001101010ShiftRegisterFXTAL/12(/6inX2mode18-bitUARTVariable
29-bitUARTFXTAL/64orFXTAL/32(/32,/16inX2mode39-bitUARTVariable
5SM2
SerialportMode2bit/MultiprocessorCommunicationEnablebitCleartodisablemultiprocessorcommunicationfeature.
Settoenablemultiprocessorcommunicationfeatureinmode2and3,andeventuallymode1.Thisbitshouldbeclearedinmode0.ReceptionEnablebit
Cleartodisableserialreception.Settoenableserialreception.
TransmitterBit8/Ninthbittotransmitinmodes2and3
Cleartotransmitalogic0inthe9thbit.Settotransmitalogic1inthe9thbit.
ReceiverBit8/Ninthbitreceivedinmodes2and3Clearedbyhardwareif9thbitreceivedisalogic0.Setbyhardwareif9thbitreceivedisalogic1.
Inmode1,ifSM2=0,RB8isthereceivedstopbit.Inmode0RB8isnotused.TransmitInterruptflag
Cleartoacknowledgeinterrupt.
Setbyhardwareattheendofthe8thbittimeinmode0oratthebeginningofthestopbitintheothermodes.
ReceiveInterruptflag
Cleartoacknowledgeinterrupt.
Setbyhardwareattheendofthe8thbittimeinmode0,seeFigure6-11.andFigure6-12.intheothermodes.
4REN
3TB8
2RB8
1TI
0RI
ResetValue=00000000bBitaddressable
Table6-15.
7SMOD1
PCONRegister
PCON-PowerControlRegister(87h
6SMOD0
5-4POF
3GF1
2GF0
1PD
0IDL
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BitNumber
7
BitMnemonicSMOD1
Description
SerialportModebit1
Settoselectdoublebaudrateinmode1,2or3.SerialportModebit0
CleartoselectSM0bitinSCONregister.SettotoselectFEbitinSCONregister.
Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.
Power-OffFlag
Cleartorecognizenextresettype.
SetbyhardwarewhenVCCrisesfrom0toitsnominalvoltage.Canalsobesetbysoftware.GeneralpurposeFlag
Clearedbyuserforgeneralpurposeusage.Setbyuserforgeneralpurposeusage.GeneralpurposeFlag
Clearedbyuserforgeneralpurposeusage.Setbyuserforgeneralpurposeusage.Power-Downmodebit
Clearedbyhardwarewhenresetoccurs.Settoenterpower-downmode.
Idlemodebit
Clearbyhardwarewheninterruptorresetoccurs.Settoenteridlemode.
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
ResetValue=00X10000bNotbitaddressable
Power-offflagresetvaluewillbe1onlyafterapoweron(coldreset.Awarmresetdoesn’taffectthevalueofthisbit.
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6.5InterruptSystem
TheTS80C51Rx2hasatotalof7interruptvectors:twoexternalinterrupts(INT0andINT1,threetimerinterrupts(timers0,1and2,theserialportinterruptandthePCAglobalinterrupt.TheseinterruptsareshowninFigure6-13.
WARNING:NotethatinthefirstversionofRCdevices,thePCAinterruptisinthelowestpriority.ThustheorderinINT0,TF0,INT1,TF1,RIorTI,TF2orEXF2,PCA.
Figure6-13.InterruptControlSystem
IPH,IP
3030
INT1
IE1
3030
Interruptpolling
sequence,decreasingfromhightolowpriorityHighpriorityinterrupt
INT0IE0
TF0
TF1
PCAIT
303030
RITITF2EXF2
IndividualEnableGlobalDisable
Lowpriorityinterrupt
EachoftheinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitintheInterruptEnableregister(SeeTable6-17.Table6-18..Thisregisteralsocontainsaglobaldisablebit,whichmustbeclearedtodisableallinterruptsatonce.
EachinterruptsourcecanalsobeindividuallyprogrammedtooneoutoffourprioritylevelsbysettingorclearingabitintheInterruptPriorityregister(SeeTable6-18.andintheInterruptPri-orityHighregister(SeeTable6-19..showsthebitvaluesandprioritylevelsassociatedwitheachcombination.
ThePCAinterruptvectorislocatedataddress0033H.AllothervectoraddressesarethesameasstandardC52devices.
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Table6-16.
IPH.x0011
PriorityLevelBitValues
IP.x0101
InterruptLevelPriority
0(Lowest
123(Highest
Alow-priorityinterruptcanbeinterruptedbyahighpriorityinterrupt,butnotbyanotherlow-prior-ityinterrupt.Ahigh-priorityinterruptcan’tbeinterruptedbyanyotherinterruptsource.
Iftwointerruptrequestsofdifferentprioritylevelsarereceivedsimultaneously,therequestofhigherprioritylevelisserviced.Ifinterruptrequestsofthesameprioritylevelarereceivedsimul-taneously,aninternalpollingsequencedetermineswhichrequestisserviced.Thuswithineachprioritylevelthereisasecondprioritystructuredeterminedbythepollingsequence.Table6-17.
7EABitNumber
IERegister
IE-InterruptEnableRegister(A8h
6EC
5ET2
4ES
3ET1
2EX1
1ET0
0EX0
BitMnemonicDescription
EnableAllinterruptbit
Cleartodisableallinterrupts.Settoenableallinterrupts.
IfEA=1,eachinterruptsourceisindividuallyenabledordisabledbysettingor
clearingitsowninterruptenablebit.PCAinterruptenablebit
Cleartodisable.Settoenable.
Timer2overflowinterruptEnablebit
Cleartodisabletimer2overflowinterrupt.Settoenabletimer2overflowinterrupt.SerialportEnablebit
Cleartodisableserialportinterrupt.Settoenableserialportinterrupt.
Timer1overflowinterruptEnablebit
Cleartodisabletimer1overflowinterrupt.Settoenabletimer1overflowinterrupt.Externalinterrupt1Enablebit
Cleartodisableexternalinterrupt1.Settoenableexternalinterrupt1.
Timer0overflowinterruptEnablebit
Cleartodisabletimer0overflowinterrupt.Settoenabletimer0overflowinterrupt.Externalinterrupt0Enablebit
Cleartodisableexternalinterrupt0.Settoenableexternalinterrupt0.
7EA
6EC
5ET2
4ES
3ET1
2EX1
1ET0
0EX0
ResetValue=00000000bBitaddressable
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Table6-18.
7-BitNumber
76543210
IPRegister
IP-InterruptPriorityRegister(B8h
6PPCBitMnemonic
-PPCPT2PSPT1PX1PT0PX0
5PT2
Description
Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.PCAinterruptprioritybitRefertoPPCHforprioritylevel.Timer2overflowinterruptPrioritybitRefertoPT2Hforprioritylevel.SerialportPrioritybit
RefertoPSHforprioritylevel.
Timer1overflowinterruptPrioritybitRefertoPT1Hforprioritylevel.Externalinterrupt1PrioritybitRefertoPX1Hforprioritylevel.
Timer0overflowinterruptPrioritybitRefertoPT0Hforprioritylevel.Externalinterrupt0PrioritybitRefertoPX0Hforprioritylevel.
4PS
3PT1
2PX1
1PT0
0PX0
ResetValue=X0000000bBitaddressable
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Table6-19.
7-BitNumber
7
IPHRegister
IPH-InterruptPriorityHighRegister(B7h
6PPCHBitMnemonic
-5PT2H
4PSH
3PT1H
2PX1H
1PT0H
0PX0H
Description
Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.PCAinterruptprioritybithigh.PPCHPPCPriorityLevel
00Lowest011011Highest
6PPCH
5PT2H
Timer2overflowinterruptPriorityHighbitPT2HPT2PriorityLevel
00Lowest011011HighestSerialportPriorityHighbitPSHPSPriorityLevel
00Lowest011011HighestTimer1overflowinterruptPriorityHighbitPT1HPT1PriorityLevel
00Lowest011011HighestExternalinterrupt1PriorityHighbitPX1HPX1PriorityLevel
00Lowest011011HighestTimer0overflowinterruptPriorityHighbitPT0HPT0PriorityLevel
00Lowest011011HighestExternalinterrupt0PriorityHighbitPX0HPX0PriorityLevel
00Lowest011011Highest
4PSH
3PT1H
2PX1H
1PT0H
0PX0H
ResetValue=X0000000b
Notbitaddressable
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6.6IdleMode
AninstructionthatsetsPCON.0causesthattobethelastinstructionexecutedbeforegoingintotheIdlemode.IntheIdlemode,theinternalclocksignalisgatedofftotheCPU,butnottotheinterrupt,Timer,andSerialPortfunctions.TheCPUstatusispreservedinitsentirety:theStackPointer,ProgramCounter,ProgramStatusWord,AccumulatorandallotherregistersmaintaintheirdataduringIdle.TheportpinsholdthelogicalstatestheyhadatthetimeIdlewasacti-vated.ALEandPSENholdatlogichighlevels.
TherearetwowaystoterminatetheIdle.ActivationofanyenabledinterruptwillcausePCON.0tobeclearedbyhardware,terminatingtheIdlemode.Theinterruptwillbeserviced,andfollow-ingRETIthenextinstructiontobeexecutedwillbetheonefollowingtheinstructionthatputthedeviceintoidle.
TheflagbitsGF0andGF1canbeusedtogiveanindicationifaninterruptoccuredduringnor-maloperationorduringanIdle.Forexample,aninstructionthatactivatesIdlecanalsosetoneorbothflagbits.WhenIdleisterminatedbyaninterrupt,theinterruptserviceroutinecanexam-inetheflagbits.
TheotherwayofterminatingtheIdlemodeiswithahardwarereset.Sincetheclockoscillatorisstillrunning,thehardwareresetneedstobeheldactiveforonlytwomachinecycles(24oscilla-torperiodstocompletethereset.
6.7Power-downMode
Tosavemaximumpower,apower-downmodecanbeinvokedbysoftware(RefertoTable6-15,PCONregister.
Inpower-downmode,theoscillatorisstoppedandtheinstructionthatinvokedpower-downmodeisthelastinstructionexecuted.TheinternalRAMandSFRsretaintheirvalueuntilthepower-downmodeisterminated.VCCcanbeloweredtosavefurtherpower.Eitherahardwareresetoranexternalinterruptcancauseanexitfrompower-down.Toproperlyterminatepower-down,theresetorexternalinterruptshouldnotbeexecutedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughfortheoscillatortorestartandstabilize.OnlyexternalinterruptsINT0andINT1areusefultoexitfrompower-down.Forthat,interruptmustbeenabledandconfiguredasleveloredgesensitiveinterruptinput.
HoldingthepinlowrestartstheoscillatorbutbringingthepinhighcompletestheexitasdetailedinFigure6-14.Whenbothinterruptsareenabled,theoscillatorrestartsassoonasoneofthetwoinputsisheldlowandpowerdownexitwillbecompletedwhenthefirstinputwillbereleased.Inthiscasethehigherpriorityinterruptserviceroutineisexecuted.
Oncetheinterruptisserviced,thenextinstructiontobeexecutedafterRETIwillbetheonefol-lowingtheinstructionthatputTS80C51Rx2intopower-downmode.
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Figure6-14.Power-DownExitWaveform
INT0INT1
XTAL1
ActivephasePower-downphaseOscillatorrestartphaseActivephase
Exitfrompower-downbyresetredefinesalltheSFRs,exitfrompower-downbyexternalinter-ruptdoesnoaffecttheSFRs.
Exitfrompower-downbyeitherresetorexternalinterruptdoesnotaffecttheinternalRAMcontent.
Note:
Ifidlemodeisactivatedwithpower-downmode(IDLandPDbitsset,theexitsequenceis
unchanged,whenexecutionisvectoredtointerrupt,PDandIDLbitsareclearedandidlemodeisnotentered.
Table6-20.
ModeIdleIdlePower-downPower-down
Thestateofportsduringidleandpower-downmode
ProgramMemoryInternalExternalInternalExternal
ALE1100
PSEN1100
PORT0PortData*FloatingPortData*Floating
PORT1PortDataPortDataPortDataPortData
PORT2PortDataAddressPortDataPortData
PORT3PortDataPortDataPortDataPortData
*Port0canforcea"zero"level.A"one"willleaveportfloating.
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6.8HardwareWatchdogTimer
TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupset.TheWDTconsistsofa14-bitcounterandtheWatchDogTimerReSeT(WDTRSTSFR.TheWDTisbydefaultdisabledfromexitingreset.ToenabletheWDT,usermustwrite01EHand0E1HinsequencetotheWDTRST,SFRlocation0A6H.WhenWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunningandthereisnowaytodisabletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset.WhenWDToverflows,itwilldriveanoutputRESETHIGHpulseattheRST-pin.
6.8.1
UsingtheWDT
ToenabletheWDT,usermustwrite01EHand0E1HinsequencetotheWDTRST,SFRloca-tion0A6H.WhenWDTisenabled,theuserneedstoserviceitbywritingto01EHand0E1HtoWDTRSTtoavoidWDToverflow.The14-bitcounteroverflowswhenitreaches16383(3FFFHandthiswillresetthedevice.WhenWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.ThismeanstheusermustresettheWDTatleastevery16383machinecycle.ToresettheWDTtheusermustwrite01EHand0E1HtoWDTRST.WDTRSTisawriteonlyregister.TheWDTcountercannotbereadorwritten.WhenWDToverflows,itwillgenerateanoutputRESETpulseattheRST-pin.TheRESETpulsedurationis96xTOSC,whereTOSC=1/FOSC.TomakethebestuseoftheWDT,itshouldbeservicedinthosesectionsofcodethatwillperiodicallybeexecutedwithinthetimerequiredtopreventaWDTreset.
TohaveamorepowerfulWDT,a27counterhasbeenaddedtoextendtheTime-outcapability,rankingfrom16msto2s@FOSC=12MHz.Tomanagethisfeature,refertoWDTPRGregisterdescription,Table6-22(SFR0A7h.
Table6-21.
WDTRSTRegister
WDTRSTAddress(0A6h
7
6X
5X
4X
3X
2X
1X
ResetvalueX
Writeonly,thisSFRisusedtoreset/enabletheWDTbywriting01EHthen0E1Hinsequence.
Table6-22.
7T4
WDTPRGRegister
WDTPRGAddress(0A7h
6T3
5T2
4T1
3T0
2S2
1S1
0S0
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AT/TS8xC51Rx2
BitNumber
76543210
BitMnemonic
T4T3T2T1T0S2S1S0
WDTTime-outselectbit2WDTTime-outselectbit1WDTTime-outselectbit0S200001111
S100110011
S0SelectedTime-out
0(214-1machinecycles,16.3ms@12MHz1(215-1machinecycles,32.7ms@12MHz0(216-1machinecycles,65.5ms@12MHz1(217-1machinecycles,131ms@12MHz0(218-1machinecycles,262ms@12MHz1(219-1machinecycles,542ms@12MHz0(220-1machinecycles,1.05s@12MHz1(221-1machinecycles,2.09s@12MHz
Reserved
Donottrytosetorclearthisbit.Description
ResetvalueXXXXX000
6.8.2
WDTduringPower-downandIdle
InPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmodetheuserdoesnotneedtoservicetheWDT.Thereare2methodsofexitingPower-downmode:byahardwareresetorviaalevelactivatedexternalinterruptwhichisenabledpriortoenteringPower-downmode.WhenPower-downisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallyshouldwhenevertheTS80C51Rx2isreset.ExitingPower-downwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptserviceroutine.
ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingofpowerdown,itisbesttoresettheWDTjustbeforeenteringpowerdown.
IntheIdlemode,theoscillatorcontinuestorun.TopreventtheWDTfromresettingtheTS80C51Rx2whileinIdlemode,theusershouldalwayssetupatimerthatwillperiodicallyexitIdle,servicetheWDT,andre-enterIdlemode.
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6.9
ONCETMMode(ONChipEmulation
TheONCEmodefacilitatestestinganddebuggingofsystemsusingTS8xC51Rx2withoutremovingthecircuitfromtheboard.TheONCEmodeisinvokedbydrivingcertainpinsoftheTS80C51Rx2;thefollowingsequencemustbeexercised:
•PullALElowwhilethedeviceisinreset(RSThighandPSENishigh.•HoldALElowasRSTisdeactivated.
WhiletheTS80C51Rx2isinONCEmode,anemulatorortestCPUcanbeusedtodrivethecir-cuitTable26.showsthestatusoftheportpinsduringONCEmode.Normaloperationisrestoredwhennormalresetisapplied.
Table6-23.
ALEWeakpull-up
ExternalPinStatusduringONCEMode
PSENWeakpull-up
Port0Float
Port1Weakpull-up
Port2Weakpull-up
Port3Weakpull-up
XTAL1/2Active
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AT/TS8xC51Rx2
7.Power-OffFlag
Thepower-offflagallowstheusertodistinguishbetweena“coldstart”resetanda“warmstart”reset.
AcoldstartresetistheoneinducedbyVCCswitch-on.AwarmstartresetoccurswhileVCCisstillappliedtothedeviceandcouldbegeneratedforexamplebyanexitfrompower-down.
Thepower-offflag(POFislocatedinPCONregister(SeeTable7-1.POFissetbyhardwarewhenVCCrisesfrom0toitsnominalvoltage.ThePOFcanbesetorclearedbysoftwareallow-ingtheusertodeterminethetypeofreset.
ThePOFvalueisonlyrelevantwithaVccrangefrom4.5Vto5.5V.ForlowerVccvalue,readingPOFbitwillreturnindeterminatevalue.
Table7-1.
7SMOD1BitNumber
7
PCONRegister
PCON-PowerControlRegister(87h
6SMOD0BitMnemonicSMOD1
5-4POF
3GF1
2GF0
1PD
0IDL
Description
SerialportModebit1
Settoselectdoublebaudrateinmode1,2or3.SerialportModebit0
CleartoselectSM0bitinSCONregister.SettotoselectFEbitinSCONregister.
Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.
Power-OffFlag
Cleartorecognizenextresettype.
SetbyhardwarewhenVCCrisesfrom0toitsnominalvoltage.Canalsobesetbysoftware.
GeneralpurposeFlag
Clearedbyuserforgeneralpurposeusage.Setbyuserforgeneralpurposeusage.GeneralpurposeFlag
Clearedbyuserforgeneralpurposeusage.Setbyuserforgeneralpurposeusage.Power-Downmodebit
Clearedbyhardwarewhenresetoccurs.Settoenterpower-downmode.
Idlemodebit
Clearbyhardwarewheninterruptorresetoccurs.Settoenteridlemode.
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
ResetValue=00X10000bNotbitaddressable
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7.1ReducedEMIMode
TheALEsignalisusedtodemultiplexaddressanddatabusesonport0whenusedwithexter-nalprogramordatamemory.Nevertheless,duringinternalcodeexecution,ALEsignalisstillgenerated.InordertoreduceEMI,ALEsignalcanbedisabledbysettingAObit.
TheAObitislocatedinAUXRregisteratbitlocation0.AssoonasAOisset,ALEisnolongeroutputbutremainsactiveduringMOVXandMOVCinstructionsandexternalfetches.DuringALEdisabling,ALEpinisweaklypulledhigh.
Table7-2.
7-BitNumber
7654321
AUXRRegister
AUXR-AuxiliaryRegister(8Eh
6-BitMnemonic
------EXTRAM
5-4-3-2-1EXTRAM
0AO
Description
Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.Reserved
Thevaluereadfromthisbitisindeterminate.Donotsetthisbit.EXTRAMbitSeeTable6-1.
ALEOutputbit
CleartorestoreALEoperationduringinternalfetches.SettodisableALEoperationduringinternalfetches.
0AO
ResetValue=XXXXXX00bNotbitaddressable
50
AT/TS8xC51Rx2
4188E–8051–08/06

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