A Fast Reconfigurable And Area EfficientEncryption Engine Using PartialReconfigurationZijia Ye, Shakith D. Fernando, Yajun Ha and Nanguang Chen.Abstract-- Partial reconfiguration (PR) allows FPGA designers to make more efficient use of available board space. At the same time, it allows adaptive hardware algorithm to be implemented since runtime reconfiguration is now possible. One of the featuresof partially reconfigured FPGAs is that the size of the bitstream is proportional to the size of the reconfigured resources. Therefore reconfiguration time is shorter if partial bitstream is used. Despite the obvious benefits of PR, there is poor support for PR at the design tools and documentation levels. A recent development in the PR software tools is the introduction of the Early-Access (EA) PR design tools. However, the EA PR software tools are still in the development stage. Applications most suited for PR include reconfigurable communications and cryptographic systems. In this paper, we describe a partially reconfigurable encryption engine using the EA PR design flow. Experimental results show that when using PR over full reconfiguration, this application reduces its configuration time overhead by 300% and achieves area savings of 7%, which is limited only by the smallest partially reconfigurable module (PRM) being implemented.Index Terms—Partial Reconfiguration, Reconfigurable Computing, Runtime Reconfiguration, Cryptographic Systems.I.I NTRODUCTIONPartial reconfiguration involves reprogramming only a subset of the FPGA device configuration memory. This can be done while the device is active or in a shutdown state. Active partial reconfiguration is the ability to reconfigure a portion of the FPGA while the remainder of the design is still in operation. This is useful for applications that may have different ways of executing a certain task, each implementation may has its own advantages, or for applications that need to change part of their designs without having to reset or completely reconfigure the whole device.Partial reconfiguration allows designers to achieve versatility, area savings and upgradeability. Another added advantage of using PR is that only a small bitstream needs to be downloaded for reconfiguration, therefore resulting in a much shorter reconfiguration time especially for large designs.Zijia Ye was with Electrical and Computer Engineering Department, National University of Singapore, Singapore 117576. (e-mail:yezijia@nus.edu.sg )Shakith D. Fernando and Yajun Ha are with the Electrical and Computer Engineering Department, National University of Singapore, Singapore 117576. (e-mail: shakith@ieee.org and elehy@nus.edu.sg)Nanguang Chen is with Division of Bioengineering and the Electrical and Computer Engineering Department, National University of Singapore, Singapore 117576. (e-mail: biecng@nus.edu.sg )Fig. 1. User ScenarioCryptographic applications are good examples of coprocessor applications. They are known to benefit significantly from spatial execution in hardware. The power dissipation and computational power of an application implemented in FPGA lie between that of software and ASIC implementations. However, you gain much flexibility from the FPGA implementation.FPGA implemented cryptographic applications will enjoy a lot of advantages from partial reconfiguration. A typical application scenario is shown in fig.1, which shows an encryption engine enabled FPGA platform with the support of partial reconfiguration. The FPGA clients of the same device type are connected to the server containing the bit streams through various communication mediums such as Ethernet, wireless LAN.At startup, the base system is preloaded to the FPGA clients. The server contains pre-generated partial bit streams for several encryption standards such as DES, 3DES. When the user application such as video application requires a DES encryption the client can download DES bitstream and partially reconfigure the Reconfigurable Encryption Module area. At a later time, when application requests 3DES, the device can download the 3DES bitstream for partial reconfiguration. The User Expansion area allows many different type of application to share this partial reconfiguration architecture. This also allows easy scalability for future encryption standards.611
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