Integrated circuits are incredibly complex devices, and few of them are perfect. Most contain subtle weaknesses and flaws, which predispose them toward eventual failure. Such components can fail catastrophically and without warning after operating perfectly for many years. Engineers have traditionally relied on quality assurance programs to uncover hidden design flaws. Operation under stressful conditions can accelerate many failure mechanisms, but not every design flaw can be found by testing.
The designer must therefore find and eliminate as many of these flaws as possible.
The layout of an integrated circuit contributes to many types of failures. If the designer knows about potential weaknesses, then safeguards can be built into the integrated circuit to protect it against failure mechanisms that can be partially or entirely.
Almost any form of friction can generate static electricity. For example, if you shuffle across a carpet in dry weather and then touch a metal doorknob, a visible spark will leap from finger to doorknob. The human body acts as a capacitor, and the act of shuffling across a carpet charges this capacitance to a potential of 10000V or more. When a finger is brought near the doorknob, the sudden discharge creates a visible spark and a perceptible electrical shock. A discharge of less than 50V will destroy the gate dielectric of a typical integrated MOS transistor. Voltages this low produce neither visible sparks nor perceptible electrical shock. Almost any human or mechanical activity can produce such low-level electrostatic discharges.
Proper handing precautions will minimize the risks of electrostatic discharge. ESD-sensitive components (including integrated circuits) should always be stored in static-shielded packaging. Grounded wrist straps and soldering irons can reduce potential opportunities for ESD discharges Humidifiers, ionizers, and antistaticmats can minimize the buildup of static charges around workstations and machinery. These precautions reduce but do not eliminate ESD damage, so manufacturers routinely include special ESD protection structures onboard integrated circuits.These structures are designed to absorb and dissipate moderate leaves of ESD energy without damage.
Special tests can measure the vulnerability of an integrated circuit to ESD. The three most common test configurations are called the human body model(HBM) employs the circuit shown in Figure.
Figure 1 Human body model
When the switch is pressed, a 150pF capacitor charged to a specified voltage discharges through a 1.5KΩ series resistor into the device under test(DUT). Ideally, each pair of pins would be independently tested for ESD susceptibility, but most testing regimens only specify a limited number of pin combinations to reduce test time. Each pair of pins is subjected to a series of positive and negative pulses; for example, three positive and three negative. After ESD stressing is complete, the part is tested to see if it still meets electrical specifications. Modern integrated circuits are routinely expected to survive 2KV HBM. Specific pins on certain parts may be required to survive up 25KV HBM.
Figure shows the circuit employed for the machine model(MM). A 200pF capacitor charged to a specified voltage discharges through a 0.5μH series inductance into the DUT. As in the HBM test, each pin combination is subjected to a predetermined series of positive and negative pulses.with only a small inductance to limit the peak current, the machine model forms a much harsher test than the human body model. New parts can survive more than 500V under machine model testing.
Figure 2 Machine model
A third ESD test called the charged device model(CDM) is gradually replacing the machine model. The charged device model places the integrated circuit package upside-down on a grounded metal plate and then charges the devices to a specified voltage through a high-value resistor. A special probe then discharges one pin to a low-impedance ground. Researchers believe that this procedure more accurately model factory handling conditions than either the human body or the machine model. CDM testing produces very brief pulses of extremely high current.. A typical testing regimen will specify 1 to 1.5KV CDM testing.
Electrostatic discharge causes several different forms of electrical damage, including dielectric rupture, dielectric degradation, and avalanche-induced junction leakage. In extreme cases, ESD discharges can even vaporize metallization or shatter the bulk silicon.
Less than 50V will rupture the gate dielectric of a typical MOS transistor. The rupture occurs in nanoseconds, requires little or no sustained current flow ,and is for all intents and purposes, irreversible. The rupture typically shorts the gate and the back gate of the damaged transistor. Capacitors that use thin insulating dielectrics are also vulnerable to this failure mechanism. An ESD discharge that strikes a pin connecting only to gates or capacitors will usually destroy these devices. If the pin also connects to diffusions, then these may avalanche before the gate oxide ruptures.
The integrity of a dielectric can be compromised by an ESD event that does not actually rupture it. The weakened dielectric can fail at any time, perhaps after hundreds or thousands of hours of flawless operation.Often the failure dose not occur until the product has been delivered to the customer. Testing cannot screen out this type of delayed ESD failure; instead, vulnerable dielectrics must be protected against excessive voltages.
Although junctions are considerably more robust than dielectrics, they can still suffer ESD damage. An avalanching junction dumps a large amount of energy into a small volume of silicon. Extreme current densities can sweep metallization through contacts to short out underlying junctions. Excessive heating can also physically damage junctions by melting or shattering the silicon. These catastrophic forms of junction damage most often manifest themselves as short circuits. Avalanched junctions that do not fail outright usually exhibit increased leakage. Unlike overstressed dielectrics, damaged junctions will usually continue to operate without further degradation. Integrated circuits are often specified to have much larger leakages than are actually observed during testing to allow some margin for ESD-induced junction leakage. However, continued exposure to ESD events will often cause a junction to degrade beyond even these relaxed limits.
All vulnerable pins must have ESD protection structures connected to their bondpads. Some pins can resist ESD and therefore do not require additional protection. Examples include pins connected to substrate and to large diffusions, such as those found in large power transistors. These large junctions may be also to disperse and absorb the ESD energy before it can damage other circuitry. Pins or devices that can withstand ESD events without the addition of ESD protection circuitry are said to be self-protecting.
Pins connecting to relatively small diffusions are vulnerable to ESD-induced junction damage. These junctions are simply not large enough to protect themselves. Certain junctions, most notably the base-emitter junctions of NPN transistors, are notoriously vulnerable to ESD damage. Avalanching the base-emitter junction of an NPN transistor permanently degrades its beta. A circuit designercan sometimes eliminate the vulnerable junctions by rearranging the circuit. Because ESD vulnerabilities are difficult to predict, cautious designers add protection devices to all pins that might be even remotely vulnerable.
Pins that connect only to gates of MOS transistors or to deposited capacitor electrodes are extremely vulnerable to ESD damage. Special input protection structures have been developed to protect dielectrics against HBM and MM events. The extremely high currents characteristic of CDM events require additional protection structures, called CDM clamps, to be placed near the vulnerable devices.
The thin emitter oxides employed in some standard bipolar processes are also susceptible to
ESD-induced rupture. This vulnerability can be eliminated by ensuring that leads that connect to external bondpads do not cross any emitter region to which they do not connect. Alternatively, ESD structures similar to those used for protecting gates can protect the vulnerable circuits. Most modern versions of the standard bipolar process employ thick emitter oxides, which eliminate the need for these precautions.
Considerable ingenuity is often required to formulate successful ESD structures for analog integrated circuits. A dozen or more protection circuits are often required to satisfy the large range of voltages and the many types of vulnerable devices found in analog circuits. The protection devices must also be evaluated to ensure that they do not interfere with the operation of the circuits they protect.
Dry etching is known to deposit charges upon the surface of the wafer. Exposed conductors can collect an electrical charge that can damage thin gate dielectrics. This failure mechanism is called process plasma-induced damage, or, more colorfully , the antenna effect. The antenna effect generates stress-induced leakage currents that can lead to either immediate or delayed failure of the overstressed dielectrics.
The exact source of the electrical charges responsible for the antenna effect is a matter of some controversy. The plasma itself contains an equal number of positive and negative particles. However, various mechanisms can cause local fluctuations in charge densities due to reactor design and AC plasma excitation, and an effect called electron shading, in which adjacent geometries block the isotropic electron flux to a greater degree than they block the anisotropic ion flux. Regardless of the precise mechanisms involved, experience has shown that both dry etching of the precise mechanisms involved experience has shown that both dry etching of conductor layers and the subsequent ash of photoresist can cause plasma-induced damage.
The impact of the antenna effect must be evaluated for the etching and ashof each conductor layer. Consider the case of polysilicon. During the initial stages of poly etching the entire surface of the wafer is covered by an unbroken sheet of ploy. Charge reach this ploy plate through all of the openings in the photoresist. Apparently, the fluctuations responsible for the antenna effect largely cancel one another out across the width of the water,for little damage occurs at this point. Partway through the etch process,the individual poly geometries separate from one another. Each geometry now picks up charge around its periphery, where the poly is exposed to the plasma. This charge is injected through the thin gate oxide. The vulnerability of a given geometry to the antenna effect therefore depends upon the ratio of its total perimeter to the active gate area beneath it. The larger this peripheral antenna ratio, the greater the risk of plasma-induced damage. Most processes define a maximum allowed peripheral antenna ratio for poly; a typical value is 100μmˉ¹.
During the final stages of photoresist ash, the entire surface of the poly pattern becomes exposed to the plasma. Each geometry now picks up charge across its entire surface and injects this charge through the thin gate oxide. The vulnerability of a given geometry to the antenna effect therefore depends upon the ratio of the total area to the active gate area beneath it. The larger this areal antenna ratio, the greater the risk of plasma-induced damage. Most processes define a maximum allowed areal antenna ratio for poly; a typical value is 500.
Each conductor layer is vulnerable to the antenna effect during etching and ash, so each layer has its own peripheral and areal antenna ratios. Consider the case of metal-2. Near the end of the etch process, the individual metal-2 geometries become separated from one anther. However, these geometries may be connected together through lower conductor layers. Therefore, the antenna effect cannot be evaluated on a geometry-by-geometry basis. Instead, one must define collections of electrically connected geometries called nodes. During the metal-2 etch, each node collects charge proportional to the metal-2 periphery exposed to the plasma and injects this charge through the active gate beneath poly geometries forming part of the node. Therefroe, the metal-2 peripheral antenna ratio of a node equals the total metal-2 periphery of the node divided by the active gate beneath the poly geometries of the node. Similarly, the evaluation of ash damage depends upon the metal-2 areal antenna ratio, defined as the total metal-2 area of a node divided by the active gate area beneath the poly geometries of the node.
A great deal of effort has been expended to understand the relationship between antenna ratios and gate dielectric damage, but much remains uncertain. Some researchers have uncovered evidence that PMOS gate oxides are considerably more sensitive to plasma-induced damage than NMOS gate oxides. Other researchers have shown that oxide isolation greatly reduces plasma-induced damage, presumably by limiting the current that can flow through any given area of gate oxide.
Any node whose antenna ratio exceeds specifications must be reworked. The exact techniques employed depend upon which layer is involved. In the case of polysilicon, the ratio can be reduced by inserting metal jumpers. Consider the case shown in Figure. This circuit contains a very long poly lead that crosses a minimum-size MOS transistor M1. The antenna ratios of this poly geometry could clearly become very large. If, however, a short metal jumper is inserted in the poly lead next to the transistor, then the single poly geometry now becomes two separate geometries. The geometry on the left (connecting to the gate of transistor M1) has relatively small antenna ratios. The geometry on the right (connecting to the source/drain of transistor M2) has zero antenna ratios because no gate oxide lies beneath it. Therefore, the addition of the metal jumper has eliminated any potential problem.
Figure 3
Metal layers are somewhat more difficult to evaluate because metal nodes can connect to diffusions that leak away the charge before it damages gate oxides. For processes that employ gate oxides thicker than about 400Ǻ, the source/drain junctions of the MOS transistors will typically avalanche before the gate oxides can be damaged. In such cases, any node that connects to a source/drain diffusion can generally be ignored when computing antenna ratios. If a metal node is found to have an excessive antenna ratio, the problem can be eliminated either by placing a jumper on a higher metal layer (as discussed previously in connection with poly), or by connecting a source/drain diffusion to the node. If the circuit dose not include a transistor connected to the node, then a small structure called a leaker can be attached instead. Figure show shows examples of NSD/P-epi leaker is preferred. This structure is essentially a diode whose anode is connected to the metal node and whose cathode is connected to the substrate. If the voltage on the node drops below the substrate potential, then the leaker will forward-bias and clamp the voltage. If the voltage on the node rises above substrate potential, then the NSD/P-epi junction will avalanche before the thick oxide is damaged.
Figure 4
Leakers for thin-oxide processes are somewhat more problematic. The avalanche voltage of an NSD/P-epi junction cannot be relied upon to protect a gate oxide much thinner than 400Ǻ. Experience has shown that nodes in thin-oxide processes can be protected by a combination of NSD/P-epi and PSD/N-well leakers. The NSD/P-epi leaker will forward-bias if the node drops below substrate potential. The PSD/N-well leaker will forward-bias if the note rises above the N-well potential, but the reverse-biased N-well/P-epi junction prevents currents from flowing through this structure during normal operation. During reactive ion etching, the light from the plasma reaction shines down on the wafer. This light encourages photogeneration within the depletion region of the charge injected onto the N-well. In order for the N-well/P-epi leaker to properly function, at least a portion of its periphery should remain uncovered by metal to a distance of at least 5-10μm outside of drawn N-well. Whenever leakers are inserted, the circuit designer should be informed of their presence so that their effect upon circuit operation can be evaluated. In most cases, the leakers will not interfere with the circuit, but it is impossible to make blanket statements about what might or might not interfere with analog circuits.
Junction isolation relies on reverse-biased junctions to block unwanted current flow. The electric fields set up by depletion regions repel majority carriers, but they cannot block the flow of minority carriers. If any isolation junction forward-biases, it will inject minority carriers into the isolation. Many of these carriers recombine, but some eventually find their way to the depletion regions isolation other devices.
Figure shows a cross section of a standard bipolar circuit. Suppose that the collector of NPN transistor Q1 connects to pin of the integrated circuit, and that the external circuitry experiences occasional transient disturbances that pull current out of this pin. If transistor Q1 is off, then these transients pull its tank below ground, forward-biasing the collector-substrate junction of Q1 and injecting minority carriers(electrons) into the substrate. Most of these carriers recombine, but some diffuse across to other tanks, such as T1.
Figure 5
The transit of minority carriers across the isolation is analogous to the flow of minority carriers through a bipolar transistor. The tank pulled below ground acts as the emitter of lateral NPN transistor Qp. The isolation and substrate act as the base of this transistor,and any other reverse-biased tank acts as a collector. Each reverse-biased tank forms a separate parasitic transistor corresponding to Qp. The betas of these parasitic lateral NPN transistors are very low because most of the minority carriers recombine in transit. The parasitic bipolar between two adjacent tanks might have a beta of 10, but the beta between two widely separated tanks might not even reach 0.001. Even such low gains can cause circuit malfunctions. Suppose that a forward-biased tank injects a minority current of 10mA into the substrate. If the parasitic associated with another tank has a beta of 0.01, then this tank will collect 100μA of current-easily enough to disrupt the operation of a typical analog circuit.
Substrate contacts cannot, by themselves, stop minority-carrier injection , since minority carriers travel by diffusion and not by drift. Minority carriers are collected only by reverse-biased junctions.However,substrate contacts still provide majority carriers to feed recombination. Since most minority carriers recombine in the isolation,substrate contacts remain necessary to prevent substrate biasing.
In some cases, minority-carrier injection can cause a circuit to latch up. Early CMOS processes suffered from a form of this malady that has since come to be called CMOS latchup. Figure shows the cross section of a portion of a CMOS die consisting of an NMOS transistor M1 and a PMOS transistor M2. In addition to these two desired MOS transistors, this layout contains two parasitic bipolar transistors. Lateral NPN transistor Qn, emitter is the source of M1, its base is the isolation, and its collector is the N-well of M2. Lateral PNP transistor Op emitter is the source of M2, its base is N-well, and its collector is the isolation. Figure shows the two parasitic bipolar transistors drawn in a more familiar fashion. In this schematic, R1 represents the well resistance of M2, and R2 represents the substrate resistance. These two resistors normally ensure that both bipolar transistors remain off. As long as this remains the case, neither parasitic conducts any current and the integrated circuit works as intended. When a transient disturbance turns on either transistor, the current flowing through this device will turn on the other parasitic as well.
Figure 6
Each transistor then supplies the other's base current. This process becomes self-sustaining if the product of the betas of transistors Qn and Qp exceeds unity. Once this happens, the circuit is said to have latched up, and it will remain in this state until power is removed. The integrated circuit can actually conducts so much current that it overheats and self-destructs. Even if this dosenot occur, latchup causes circuit malfunctions and excessive supply current consumption.
CMOS latchup can be triggered in one of two ways. If the source of NMOS transistor M1 is pulled below ground, it will inject minority carriers(electrons) into the substrate, turning on parasitic transistor Qn. This transistor will then turn on Qp. Alternatively, the source of PMOS transistor M2 may be pulled above the well. It will then inject minority carriers (holes) into the well and will turn on parasitic transistor Qp. This transistor then turns on Qn. Some authors explain CMOS latchup by comparing the four regions involved (PMOS source, PMOS backgate, NMOS backgate, NMOS source) to the four-layer PNPN device called a silicon-controlled rectifier (SCR). Electrically, an SCR is equivalent to the coupled bipolar transistors of Figure. Therefore the SCR model of CMOS latchup is essentially the same as the bipolar model presented here.
The obvious way to stop CMOS latchup consists of reducing the beta of either or both parasitic transistors. If the product of these betas is less than unity, then latchup cannot occur. This is usually achieved by increasing layout spacing, which in turn increases the width of the neutral base regions of the parasitic lateral transistors. Alternatively, the amount of dopant present in the neutral base region of one(or both) parasitic transistors may be increased. Both of these approaches increase the Gum number of one or both transistors and reduce the beta product.
Although many CMOS processes claim immunity to latchup, these claims are true only in a somewhat narrow sense. The PNPN structure inherent in such a process lacks sufficient gain to establish regenerative feedback, but minority-carrier injection still occurs. The collected carriers can still cause circuit malfunctions, and if positive feedback exists in the circuit, these malfunctions can still cause a for of latchup. Thesignificance of this observation is frequently underestimated. Any integrated circuit that experiences unanticipated minority-carrier injection can potentially latch up. Even if it dose not actually do so, it is still likely to malfunction. Not only do electrons injected into the substrate pose a potential threat, but so do holes unintentionally injected into wells or tanks.
Fundamentally, there are four ways to defeat minority-carrier injection: (1) eliminate the forward-biased junctions that cause the problem, (2) increase the spacing between components, (3) increase doping concentrations, and (4) provide alternate collectors to remove unwanted minority carriers. All of these techniques provide some benefit, and incombination they can correct almost any minority-carrier injection problem.
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