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FPGA作业-序列检测器(10010)状态机划分

发布时间：2023-02-03 14:59:19 来源：文档文库

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序列检测器（10010），状态机划分
一、程序设计
module string1001(clk, X, rst, Z; input clk, X, rst; output Z; parameter S0 = 2'b00, S1= 2'b01,
S2 = 2'b10,SA = 2'b11,S3 = 2'b00, S4 = 2'b01, S5 = 2'b10,SB = 2'b11; reg [1:0] state1,state2;
reg [1:0] next_state1,next_state2; always @(posedge clk if (rst state1 <= S0; else

state1 <= next_state1; always @(posedge clk state2<=next_state2; always @(state1 or X

if(state1!=SA case(state1
S0:if(X next_state1 = S1;else next_state1 = S0;
S1:if(X next_state1 = S1;else next_state1 = S2;
S2:if(X next_state1 = S1;
else
begin
next_state2=S3;
next_state1=SA;

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